IPC-CM-770D-1996 - 第64页

IPC-CM-770 Januaty 1996 i * (Bare chlp) b'acxnged chIr:) 1 4 Autornatlc wlre bondlng (10 111llb) automated Fl~p ch p D& r ' ne bondlng (10 r,'$ Chlp carrler (4 TIIS) FI p CIIP Ilpan snacllg) (20 40 or …

January

1996

IPC-CM-770

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Figure 13-4 Ball Grid Array Package Outline

3-27

Licensed by Information Handling Services

IPC-CM-770

Januaty

1996

(Bare chlp)

b'acxnged

chIr:)

Autornatlc

wlre

bondlng

(10

111llb)

automated Fl~p

bondlng

(10

r,'$

Chlp carrler

TIIS)

CIIP

Ilpan snacllg)

(20

1%)

(50

158

ouIlrie IC

(53

IS1

pat:

(100

r's!

chip encapsulatlon

Surface

mountlng

Surface mount

Througi-

bole

mount

IPC-1-00383

Figure 14-1 Packaging and Assembling Integrated Circuits

interconnection in one step. Also accommodates semiau-

tomatic bonding operations.

Ruggedness: Chips are somewhat enclosed.

Inspection: Readily possible to check bonding for some

devices.

Readily possible to pretest and pre-assembly bum-in.

The disadvantages of using face-bonded chips are:

Availability: Relatively few semiconductors come in face-

bonded form.

Inspection: Some devices such as flip chips do not facili-

tate inspection.

Cost: Cost more than back-bonded chips, extra processing

required by IC manufacturer.

Heat Transfer: Poor heat dissipation, connection through

leads only.

14.1.3 Special Chip Configuration

Special chip con-

figuration, such as flip chips and beam leads, require differ-

ent bonding technologies. Flip chip, or face down, and

beam lead bonding utilize techniques, such as ultrasonic

bonding, welding and soldering.

The original flip chip concept employed small, solder-

coated copper balls sandwiched between the chip termina-

tion lands and the appropriate lands on the interconnecting

sub- strate, as shown in Figure 14-2A. The resultant solder

joints were made when the unit was exposed to an elevated

temperature. However, the handling and placement of the

small-diameter balls was extremely difficult and the opera-

tion was costly.

A more advanced technique is shown in Figure 14-2B. In

this concept a raised metallic bump or lump, usually solder,

is provided on the chip termination land. This is normally

done on all lands of all of the chips while they are still in

Integrated-clrcult chlp

Termlnal pad

Solder coaled

copper ball

Substrate

(a)

Integrated-clrcult chlp

Substrate

(b)

lntegrated~clrcult chlp

Terminal pad

C-Termlnal pad

Alternate method plated

substrate bump

IPC-1-00348

gure 14-2 Face-down Bonding Concepts

the large wafer form. The individual chip is then aligned to

the appropriate circuitry on the substrate and bonded in

place using reflow soldering techniques. In this way, the

interconnection bonds between the chip and the substrate

are made simultaneously, thus reducing fabrication costs.

A solution to the availability problem is found in using the

concept in Figure 14-2C. In this approach the bump is pro-

duced as a part of the circuitry on the interconnecting sub-

strate, rather than as a part of the chip. Thus, the COB

assembler can use any of the devices that are available in

bare-chip form.

The other major special chip configuration is beam lead,

3-28

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January 1996 IPC-CM-770

Collector beam

lead

Base beam

lead

Emltter beam

lead

IPC-1-00349

Figure 14-3 Beam-lead Transistor

Table 14-1 Various Chip Bonding Adhesive Types

TY Pe

Limitations

Advantages

Phenolics

relatively high outgassing, some decomposition

Not suitable for tempertures above 120"C, Easy to rework

Polyurethanes

corrosive, difficult to process at low tempertures

Used mostly for structural applications, possibly Very high bond strength

Polyamides

Easy to rework High moisture absorption, high outgassing,

variations in electrical insulation properties,

especially when exposed to high humidity

vehicles

Polyimides

of thermal expansion

purity, low outgassing

Moderate-to-poor bond strength, High coefficient High-temperature stability, easy to rework, high Silicones

High cure temperatures, require solvents as Very-high temperature stability

Epoxies

Some are easy to rework by thermomechanical Depending on type of curing agent used and

means, some are low outgassers, easy to degrees of cure: outgassing, catalyst leaching,

process, can be filled to 60-70 percent with a

variety of conductive or nonconductive fillers

corrosivity

bond strengths elevated temperature

150°C) conditions

Cyanoacrylates

Bond strengths often degrade under moist or Very rapid setting(=lO sec), give very high initial

Table 14-2 Wire Bonding Feature Limits (see Figure 14-4)

Bonding Process

B (min) A (min)

Gold Wire Bonding

Termocompression

Thermosonic

0.01 mm

[0.004

in.]

[0.004

in.]

0.01 mm 0.01 mm

[0.004

in.]

[0.004.

in.]

0.01 mm

Aluminum Wire Bonding

0.01 mm

Ultrasonic

10.004

in.]

Figure

14-3.

In this technology, the lead is produced with

plating techniques during the chip fabrication processing

on the undiced wafer.

14.3.2 Land Patterns

A prime factor that should be kept

in mind is that the exact placement of components is not

always possible. Ideally, parts should be able to be mislo-

cated by up to

0.25

mm and up to

10"

in rotation.

Automatic wire/lead bonders require special layout consid-

erations to optimize their operational efficiency. Although

the following information pertains specifically to chip and

wire technology, similar considerations apply to the other

COB technologies.

(max)

D (min)

(min)

0.75mm 0.63 mm

[0.030 in. [0.025 in.]

0.4

mm 1

0.75 mm 0.63mm

0.25mm

[0.010 in.]

0.25mm

[0.010 in.]

0.25 mm

[0.010 in.]

D(max)

2.5 mm

[0.100 in.]

2.5 mm

[0.100 in.]

2.5 mm

[0.100 in.]

These special considerations include:

Uniform wireAead length

Preferred wire/lead lengths of

1.5

mm, but not greater

than

2.5

mm.

A narrow range of chip to board "step down."

A uniform, homogeneous bonding surface.

Chip attachment land should be at least

0.5

mm larger

that the chip on all four sides.

The location of multiple chips on the board should be

equally spaced and on the same axis.

The bonding land should be at least

0.5

mm from the chip

attachment land.

3-29

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