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MSP-GANG.dll Description www.ti.com 106 SLAU358Q – September 2011 – Revised October 2019 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Dynamic Link Library for MSP-GANG Programmer #d…
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MSP-GANG.dll Description
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Dynamic Link Library for MSP-GANG Programmer
#define SECONDCODE_FILE_INDEX 3
#define CODE2_FILE_INDEX 4
#define CFG_USE_SCRIPT_FILE 45
// disable 0
// enable 1
#define CFG_IMAGE_NO 46
//image number - 0...9
#define CFG_RESETTIME 47
#define RESET_10MS_INDEX 0
#define RESET_100MS_INDEX 1
#define RESET_200MS_INDEX 2
#define RESET_500MS_INDEX 3
#define RESET_CUSTOM_INDEX 4
#define RESET_MAX_INDEX RESET_CUSTOM_INDEX
#define CFG_PROJECT_SOURCE 48
#define INTERACTIVE_MODE 0
#define FROM_IMAGE_MEMORY_MODE 1
#define STANDALONE_MODE 2
#define FROM_IMAGE_FILE_MODE 3
#define PROJECT_SOURCE_MAX_INDEX FROM_IMAGE_FILE_MODE
#define CFG_COPY_CFG_FROM_MEMORY_EN 49
// Direct (eg. Interactive) 0
// From Image memory 1
#define CFG_RUNNING_SCRIPT_MODE 50
#define RUNNING_SCRIPT_NONE 0
#define RUNNING_SCRIPT_ONLINE 1
#define RUNNING_SCRIPT_OFFLINE 2
#define CFG_VCC_SETTLE_TIME 51
// Vss settle time in step 20 ms. Range 0...200 ( time 0...4000 ms)
#define CFG_JTAG_UNLOCK_EN 52
// disable 0
// enable 1
#define CFG_CODE2_FILE_EN 53
// disable 0
// enable 1
#define CFG_BSL_FIRST_PASSWORD 54
#define BSL_ANY_PASSW 0
#define BSL_PASSW_FROM_CODE_FILE 1
#define BSL_PASSW_FROM_PASSWORD_FILE 2
#define BSL_EMPTY_PASSW 3
#define CFG_DEFINED_RETAIN_DATA_EN 55
// disable 0
// enable 1
#define CFG_DEFINED_RETAIN_START_ADDR 56
//address must be even
#define CFG_DEFINED_RETAIN_END_ADDR 57
//address must be odd
#define DEFINED_RETAIN_DATA_MAX_SIZE 0x40
// END_ADDR - START_ADDR + 1 <= DEFINED_RETAIN_DATA_MAX_SIZE
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Dynamic Link Library for MSP-GANG Programmer
#define CFG_SECURE_CODE_SOURCE 58
enum {USER_SOURCE=0, FILE_SOURCE=1};
#define CFG_MSP432_CLR_LOCKING_OPTIONS 59
#define MSP432_CLR_LOCKING_INFOA_BIT 0x01
#define MSP432_CLR_LOCKING_BSL_BIT 0x02
#define MSP432_CLR_LOCKING_MASK ( MSP432_CLR_LOCKING_INFOA_BIT |
MSP432_CLR_LOCKING_BSL_BIT )
#define CFG_WRDEF_EXCLUDE_SECTIONS 60
// mask for 4 Read_Defined excluded sections disable->0, enable->1
// bit 0 -> 0x01 section 1
// bit 1 -> 0x02 section 2
// bit 2 -> 0x04 section 3
// bit 3 -> 0x08 section 4
#define CFG_RDDEF_EXCLUDE_SECTIONS 61
// mask for 4 Read_Defined excluded sections disable->0, enable->1
// bit 0 -> 0x01 section 1
// bit 1 -> 0x02 section 2
// bit 2 -> 0x04 section 3
// bit 3 -> 0x08 section 4
#define CFG_WRDEF_EXCLUDE_S1_START_ADDR 62
#define CFG_WRDEF_EXCLUDE_S1_END_ADDR 63
#define CFG_WRDEF_EXCLUDE_S2_START_ADDR 64
#define CFG_WRDEF_EXCLUDE_S2_END_ADDR 65
#define CFG_WRDEF_EXCLUDE_S3_START_ADDR 66
#define CFG_WRDEF_EXCLUDE_S3_END_ADDR 67
#define CFG_WRDEF_EXCLUDE_S4_START_ADDR 68
#define CFG_WRDEF_EXCLUDE_S4_END_ADDR 69
#define CFG_RDDEF_EXCLUDE_S1_START_ADDR 70
#define CFG_RDDEF_EXCLUDE_S1_END_ADDR 71
#define CFG_RDDEF_EXCLUDE_S2_START_ADDR 72
#define CFG_RDDEF_EXCLUDE_S2_END_ADDR 73
#define CFG_RDDEF_EXCLUDE_S3_START_ADDR 74
#define CFG_RDDEF_EXCLUDE_S3_END_ADDR 75
#define CFG_RDDEF_EXCLUDE_S4_START_ADDR 76
#define CFG_RDDEF_EXCLUDE_S4_END_ADDR 77
#define CFG_RD_TLV_EN 78
#define CFG_SERIALIZATION_EN 80
// disable 0
// enable 1
#define CFG_SN_ADDRESS_IN_MEMORY 81
//address must be even
#define CFG_SN_DATA_SIZE_IN_BYTES 82
//Size must be even 2...16
#define SN_DATA_MAX_SIZE 16
#define CFG_SN_REMOVE_CODE_FROM_SN_LOCATION 83
// disable 0
// enable 1
#define CFG_SN_SOURCE 84
#define SN_SOURCE_DEFINED 0
#define SN_SOURCE_FROM_FILE 1
// 0 - defined
// 1 - from file
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#define CFG_SN_FORMAT_IN_MEMORY 85
#define SN_FORMAT_LSB_FIRST 0
#define SN_FORMAT_MSB_FIRST 1
#define CFG_SN_DATA_INCREMENT 86
#define CFG_INIT_SN_DATA_0 87
//Bits 0-31 of the SN init data
#define CFG_INIT_SN_DATA_1 (CFG_INIT_SN_DATA_0+1)
//Bits 32-63 of the SN init data
#define CFG_INIT_SN_DATA_2 (CFG_INIT_SN_DATA_0+2)
//Bits 64-91 of the SN init data
#define CFG_INIT_SN_DATA_3 (CFG_INIT_SN_DATA_0+3)
//Bits 92-127 of the SN init data
#define CFG_SN_DESTINATION 91
#define NUMBER_TO_FLASH 0
#define NUMBER_TO_MAC_REG 1
#define CFG_MPU_IPE_WR_LOCKED 92
// disable 0
// enable 1
#define CFG_MPU_IPE_WR_UNLOCKED 93
// disable 0
// enable 1
#define CFG_MPU_IPE_RD_UNLOCKED 94
// disable 0
// enable 1
#define CFG_MPU_IPE_START_ADDR 95
#define CFG_MPU_IPE_END_ADDR 96
#define CFG_ADDITIONAL_COMPORT_NO 200
// 0 - disable (default)
// 1-255 added COM port number 1-255
// MSP432P protection configuration
#define CFG_MSP432_MB_CMD 300
#define CFG_MSP432_MB_JTAG_SWD_LOCK_SECEN 301
#define CFG_MSP432_MB_JTAG_SWD_LOCK_AES_INIT_VECT0 302
#define CFG_MSP432_MB_JTAG_SWD_LOCK_AES_INIT_VECT1 303
#define CFG_MSP432_MB_JTAG_SWD_LOCK_AES_INIT_VECT2 304
#define CFG_MSP432_MB_JTAG_SWD_LOCK_AES_INIT_VECT3 305
#define CFG_MSP432_MB_JTAG_SWD_LOCK_AES_SECKEYS0 306
#define CFG_MSP432_MB_JTAG_SWD_LOCK_AES_SECKEYS1 307
#define CFG_MSP432_MB_JTAG_SWD_LOCK_AES_SECKEYS2 308
#define CFG_MSP432_MB_JTAG_SWD_LOCK_AES_SECKEYS3 309
#define CFG_MSP432_MB_JTAG_SWD_LOCK_AES_SECKEYS4 310
#define CFG_MSP432_MB_JTAG_SWD_LOCK_AES_SECKEYS5 311
#define CFG_MSP432_MB_JTAG_SWD_LOCK_AES_SECKEYS6 312
#define CFG_MSP432_MB_JTAG_SWD_LOCK_AES_SECKEYS7 313
#define CFG_MSP432_MB_JTAG_SWD_LOCK_UNENC_PWD0 314
#define CFG_MSP432_MB_JTAG_SWD_LOCK_UNENC_PWD1 315
#define CFG_MSP432_MB_JTAG_SWD_LOCK_UNENC_PWD2 316
#define CFG_MSP432_MB_JTAG_SWD_LOCK_UNENC_PWD3 317
#define CFG_MSP432_MB_SEC_ZONE0_SECEN 318
#define CFG_MSP432_MB_SEC_ZONE0_START_ADDR 319
#define CFG_MSP432_MB_SEC_ZONE0_LENGTH 320
#define CFG_MSP432_MB_SEC_ZONE0_AESINIT_VECT0 321
#define CFG_MSP432_MB_SEC_ZONE0_AESINIT_VECT1 322
#define CFG_MSP432_MB_SEC_ZONE0_AESINIT_VECT2 323