IPC-SM-782A 表面安装设计和焊盘设计标准(带BGA).pdf - 第43页

boards may favor the lands only (pad cap) concept. The pad cap concept has two yield improvement beneﬁts: 1) no ﬁne conductor geometries on the outer layers because they are buried in the inner layers where conductor wid…

exposed or damaged, and rough edges must be sanded

lightly to remove burrs and rough fabric particles. See Fig-

ure 3–30.

The routed slot and tab pattern is widely used for panel

construction and break-away tab extensions. Routing is

more precise than scoring, and edge surfaces are smooth,

but the break-away ‘‘tab’’ points will require consideration.

Tabs can be cut and ground ﬂush with the board edge or

pre-drilled in a pattern. The drilled pattern furnishes a low

stress break point on the ‘‘tab’’. If the hole pattern is

recessed within the board edge, secondary sanding or

grinding can be bypassed. See Figures 3–31 and 3–32.

3.6.4.7 Artwork Compensation and Scaling

Artwork

compensation and scaling are two adjustments that are

made by the printed board fabricator to the original printed

board artwork ﬁlm or CAD data prior to beginning the fab-

rication process.

Modiﬁcations are made to the artwork feature sizes to com-

pensate for the etch factor that occurs when etching away

unwanted copper from the inner and outer layers of a

printed board. The outer layers require more compensation

than inner layers due to the overplating of copper and other

metals that form the copper protection during the etching

process. This is one of the reasons conductor width control

on outer layers of printed boards can be substantially more

difficult than inner layer conductor width control.

Scaling is an adjustment made to the artwork by the fabri-

cator offset printed board material shrinkage, which is in

the range of 8–13 µm [0.00035–0.0005 in] per 25 mm, that

occurs during the lamination process. When the annular

ring requirements fall below a nominal 0.25 mm [0.010 in],

artwork scaling will typically be invoked by the printed

board fabricator.

3.7 Outer Layer Finishes

3.7.1 Soldermask vs. Lands Only

In referring to the

outer layers of the multilayer PB, there is a dramatic dif-

ference between the concepts of soldermask and having no

conductors on the outer layers. Conventional SMT design

rules allow routing conductors on the outer layers, running

the conductors between Surface Mount lands, then apply-

ing soldermask to cover the conductors and leave the lands

exposed. For high density SMT applications, the conduc-

tors and clearances on the outer layers are generally in the

0.15–0.2 mm [0.006–0.008 in] range.

Aside from the soldermask registration, maintaining preci-

sion conductor width control on the outer layers is signiﬁ-

cantly more difficult than on the inner layers. Outer layer

conductor integrity can be a cause of poor fabrication

yields. The soldermask rule is very simple: the conductors

between lands must be covered with soldermask, while the

lands must not have any soldermask on them. When using

smaller geometries, adding the Standard Fabrication Allow-

ance of 0.2 mm [0.008 in] can make soldermask registra-

tion very difficult.

Given the two distinct yield difficulties of conductor width

control and soldermask application, board manufacturers

with experience in high density SMT printed conductor

IPC-782-3-30

Figure 3–30 Conductor clearance for V-groove scoring

90°

▼

Break Line

▼

60°

▼

Conductors Must

Be Clear of Score

Zone

90° Score

Option

60° Score

Option

▲

IPC-SM-782A December 1999

电子技术应用　　　　　ｗｗｗ．ＣｈｉｎａＡＥＴ．ｃｏｍ

boards may favor the lands only (pad cap) concept. The

pad cap concept has two yield improvement beneﬁts: 1) no

ﬁne conductor geometries on the outer layers because they

are buried in the inner layers where conductor width con-

trol is signiﬁcantly easier, and 2) the need for soldermask

is reduced or eliminated because there are no small spaces

to protect from the soldering process.

In general, an 8-layer printed board, with lands only on the

outer layer, is similar in cost to a 6-layer printed board with

solder mask, assuming both have SMT geometries. The

primary reason for this is that some PB fabricators are

realizing about a 12% yield improvement by not having the

ﬁne line conductors on the outer layers.

The beneﬁts of pad caps continue into the assembly pro-

cess by increasing yields through the reduction of solder

shorts or bridging. The pad cap concept provides 100%

testability, thus testing beneﬁts are both economical and

practical.

IPC-782-3-31

Figure 3–31 Breakaway (routed pattern)

[75mm 3.0] TYP

Approximately

Center to Center Spacing

▼

▼ ▼

▼

0.4mm

[0.159]

Tooling Hole

5.0mm

[0.197]

10mm [0.40]

Depending on PWB

Outline Design

5.0mm

[0.197]

12.5mm

[0.50]

Breakaways

▼

1.25mm [0.050] TYP

0.8mm [0.031]

Dia Thru XX PL

▼

2.25mm

[0.90]

1.2mm [0.047]

R TYP

4.5mm

[0.180]

REF

Detail of Breakaway

▼

0.4mm

[.016]

LOW STRESS (MOUSE BITE) BREAKAWAY

IPC-782-3-32

Figure 3–32 Routed slots

Break Line

▼

December 1999 IPC-SM-782A

电子技术应用　　　　　ｗｗｗ．ＣｈｉｎａＡＥＴ．ｃｏｍ

3.7.2 Soldermask Issues

Rework of Surface Mount

Assemblies due to soldermask related defects is cited as a

major cause of problems by assembly people. Following

are two classes of assembly problems caused by improp-

erly applied soldermask: 1) soldermask on the component

mounting lands; 2) insufficient soldermask coverage of

unrelated circuit features in close proximity to the compo-

nent mounting land.

Regarding soldermask on the lands and assuming that the

solderability requirements of the component leads and

board mounting lands have been met, the solder paste com-

position, viscosity, and aging are within limits, and the

thermal proﬁle of the reﬂow oven is correct, the only other

variable which could be detrimental to good solder joint

integrity is soldermask material on the lands. If there is any

soldermask (even if invisible to the naked eye) on the lands

during reﬂow, solder joint integrity can be lost through

improper surface wetting.

The second class of assembly defects is created when there

is insufficient soldermask coverage of circuitry in close

proximity to the component mounting land leading to sol-

der shorts or bridging. The majority of SMT designs incor-

porate very small geometries of 0.15–0.2 mm [0.006–

0.008 in] conductors and spacing on the outer layers of the

printed board. Designing a soldermask to cover a 0.15 mm

[0.006 in] conductor and only half of the 0.15 mm [0.006

in] space between the conductor and the land is easy

enough to accomplish during design. However, photo

imaged soldermask will overcome most of the above issues

(see Section 3.7.4).

Close examination of solder bridging on Printed Board

Assemblies will reveal that most of the bridging actually

occurs between the component leads above the surface of

the PB, and not between the lands on the board. Even if a

soldermask has sufficient resolution and registration to pro-

vide a solder dam between lands, it still may not prevent

bridging between the leads. Soldermask should not, and

can not, be expected to compensate for deﬁciencies in the

soldering process if the assembly uses Fine Pitch compo-

nents.

3.7.3 Solder Mask Clearances

A soldermask may be

used to isolate the land pattern from other conductive fea-

tures on the board such as vias, lands or conductors. Where

no conductors run between lands, a simple gang mask can

be used as shown in Figure 3–33. Tolerance requirements

for this design can generally be met by a screen printed

soldermask. A 0.38 mm [0.015 in] spacing could be accept-

able. Any class of solder mask per IPC-SM-840 could be

applied. The most commonly chosen solder mask would be

a Class 3 mask because of its higher temperature character-

istics. Due to the close proximity of the solder mask to the

land pattern, care must be taken in choosing a mask that

has low ﬂow and low solvent-bleed characteristics to avoid

land pattern contamination.

For land pattern designs with routed conductors between

lands (Figure 3–34) the tolerance requirement would

require a photo-imageable soldermask. This is necessary

because of the tight tolerance needed to cover the conduc-

tors without encroaching on the land area. A 0.08 to 0.125

mm [0.003 to 0.005 in] clearance is required with this type

of design.

3.7.4 Soldermask Types

Solder mask coatings are avail-

able in two forms, liquid and dry ﬁlm. The polymer mask

material is applied using several process methods and are

furnished in varying thicknesses. As an example, liquid

materials will have a ﬁnished thickness of 0.02 to 0.025

mm while the dry ﬁlm products are supplied for 0.08–0.10

IPC-782-3-33

Figure 3–33 Gang solder mask window

Solder Mask

Land

Gang

▼

IPC-782-3-34

Figure 3–34 Pocket solder mask windows

Land

Conductor

▼

Pocket

IPC-SM-782A December 1999

电子技术应用　　　　　ｗｗｗ．ＣｈｉｎａＡＥＴ．ｃｏｍ