IPC-A-610C(电子组装件的验收条件) - 第359页
1 W T 12-171 12-172 12-94 IPC-A-610C
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NOTE: Appendix A is quoted from IPC-2221 Generic Stan-
dard on Printed Board Design (February 1998) and is pro-
vided for information only. It is current as of publication
date of this document. The user has the responsibility to
determine the most current revision level of IPC-2221 and
specify the specific application to their product. Paragraph
and table numbers are from IPC-2221.
The following statement from IPC-2221 applies to this Appen-
dix ONLY: 1.4 Interpretation – ‘‘Shall,’’ the imperative form
of the verb, is used throughout this standard [IPC-A-610C
Appendix A] whenever a requirement is intended to express a
provision that is mandatory.
IPC-2221 –
6.3 Electrical Clearance Spacing between
conductors on individual layers should be maximized when-
ever possible. The minimum spacing between conductors,
between conductive patterns, layer to layer conductive
spaces (z-axis), and between conductive materials (such as
conductive markings or mounting hardware) and conductors
shall be in accordance with Table 6-1, and defined on the
master drawing. For additional information on process allow-
ances effecting electrical clearance, see Section 10.
When mixed voltages appear on the same board and they
require separate electrical testing, the specific areas shall be
identified on the master drawing or appropriate test specifica-
tion. When employing high voltages and especially AC and
pulsed voltages greater than 200 volts potential, the dielectric
constant and capacitive division effect of the material must be
considered in conjunction with the recommended spacing.
For voltages greater than 500V, the (per volt) table values
must be added to the 500V values. For example, the electri-
cal spacing for a Type B1 board with 600V is calculated as:
600V - 500V = 100V
0.25 mm + (100V x 0.0025 mm)
= 0.50 mm clearance
When, due to the criticality of the design, the use of other
conductor spacings is being considered, the conductor spac-
ing on individual layers (same plane) shall be made larger
than the minimum spacing required by Table 6-1 whenever
possible. Board layout should be planned to allow for the
maximum spacing between external layer conductive areas
associated with high impedance or high voltage circuits. This
will minimize electrical leakage problems resulting from con-
densed moisture or high humidity. Complete reliance on coat-
ings to maintain high surface resistance between conductors
shall be avoided.
IPC-2221 –
6.3.1 B1-Internal Conductors Internal
conductor-to-conductor, and conductor-to-plated-through
hole electrical clearance requirements at any elevation. See
Table 6-1.
IPC-2221 –
Table 6-1 Electrical Conductor Spacing
Voltage
Between
Conductors
(DC or AC
Peaks)
Minimum Spacing
Bare Board Assembly
B1 B2 B3 B4 A5 A6 A7
0-15 0.05 mm 0.1 mm 0.1 mm 0.05 mm 0.13 mm 0.13 mm 0.13 mm
16-30 0.05 mm 0.1 mm 0.1 mm 0.05 mm 0.13 mm 0.25 mm 0.13 mm
31-50 0.1 mm 0.6 mm 0.6 mm 0.13 mm 0.13 mm 0.4 mm 0.13 mm
51-100 0.1 mm 0.6 mm 1.5 mm 0.13 mm 0.13 mm 0.5 mm 0.13 mm
101-150 0.2 mm 0.6 mm 3.2 mm 0.4 mm 0.4 mm 0.8 mm 0.4 mm
151-170 0.2 mm 1.25 mm 3.2 mm 0.4 mm 0.4 mm 0.8 mm 0.4 mm
171-250 0.2 mm 1.25 mm 6.4 mm 0.4 mm 0.4 mm 0.8 mm 0.4 mm
251-300 0.2 mm 1.25 mm 12.5 mm 0.4 mm 0.4 mm 0.8 mm 0.8 mm
301-500 0.25 mm 2.5 mm 12.5 mm 0.8 mm 0.8 mm 1.5 mm 0.8 mm
> 500
See para. 6.3
for calc.
0.0025 mm
/volt
0.005 mm
/volt
0.025 mm
/volt
0.00305 mm
/volt
0.00305 mm
/volt
0.00305 mm
/volt
0.00305 mm
/volt
B1 - Internal Conductors
B2 - External Conductors, uncoated, sea level to 3050 m
B3 - External Conductors, uncoated, over 3050 m
B4 - External Conductors, with permanent polymer coating (any elevation)
A5 - External Conductors, with conformal coating over assembly (any elevation)
A6 - External Component lead/termination, uncoated
A7 - External Component lead termination, with conformal coating (any elevation)
Appendix A
Electrical Conductor Spacing
A-1IPC-A-610C January 2000