IPC-TM-650 EN 2022 试验方法-- - 第752页

5.3 Dat a Handling and Analysis 5.3.1 Lognormal plots are recommended for plotting pe r- cent of samples above an insulation resistance value, versus insulation res istance. Use the log va lue of the insulation resis- ta…

5.2 Test Procedures

5.2.1 Environmental Test Chamber Controls

Tight con-

trol of the test chamber temperature and humidity is critical for

this test method. A difference of 5% relative humidity can

result in a 0.5 to 1.0 decade difference in measured resis-

tance. If condensation occurs on the test specimens within

the environmental chamber while the samples are under volt-

age, other dendritic growth can occur. Water spotting may

also be observed in some ovens where the air flow in the

chamber is from back to front, when water condensation on a

cooler oven window can be blown around the oven as very

small droplets that deposit on test specimens. This contrib-

utes to dendritic growth.

5.2.1.1 Test Interrupt

In the event that the environmental

test chamber deviates from the controlled environment, a

drop in relative humidity may be permitted for short periods

not to exceed 15 minutes, provided that the chamber air tem-

perature does not exceed board temperature by more than

5 °C. Boards or coupons being added to a chamber

pre-heated to the temperature of the chamber.

5.2.2 Resistance Measurements

Measure the insulation

resistance of each test board daisy-chain net using 50 VDC

per second rate of rise and minimum hold time of 60 seconds

at 100 VDC test voltage. The polarity of the bias (conditioning)

voltage and the polarity of the test (measurement) voltage

always be the same. 100 VDC applied voltage is used

as the test voltage for insulation resistance measurements.

5.2.3

After initial insulation resistance measurements are

taken, close the environmental test chamber and allow the

test boards to stabilize for 96 hours (± 30 minutes) at the

specified 65 ± 2 °C [149 ± 3.6 °F] or 85 ± 2 °C [185 ± 3.6 °F]

with 87 +3/-2% relative humidity and no bias applied. After the

96 hour (± 30 minutes) stabilization period, insulation resis-

tance measurements

be made between each daisy-

chain net and ground.

5.2.4

Ensure that all test board samples are connected and

that the appropriate current limiting resistor is in series with

each corresponding test circuit. Then, connect the test

boards to the power supply to begin the T/H/B portion of the

CAF testing.

5.2.5

Verify that the appropriate voltage bias is being

applied for the duration of the test. For comparing the CAF

resistance of different laminate materials and processes, the

10 VDC and 100 VDC bias are standards. For correlating test

results to expected life in the field, the bias voltage selected

should be two times the maximum operating voltage differen-

tial for a given application. Higher voltage almost linearly

affects time to failure, however higher voltage may offset the

impact of humidity due to localized heating and should be

avoided since humidity is a key part of the failure mechanism.

5.2.6

The bias polarity should always be the same as the

polarity used when measuring the insulation resistance after

the 96-hour stabilization period.

5.2.7

It is recommended that resistance monitoring mea-

surements be taken every 24 to 100 hours of bias (condition-

ing) voltage during the duration of the test, ensuring that the

polarity of the insulation measurement voltage and the bias

voltage are always the same. Decade drops in resistance,

observed when these intermediate measurements are taken,

also count as failures and improve the accuracy of the test

since CAF filaments are very thin and are easily destroyed.

Also when over 50% of the parts have failed, the test can be

stopped. As CAF forms, the voltage delivered across the CAF

failure site will drop as the resistance decreases. This

becomes significant as the resistance of the net approaches

the resistance of the current-limiting resistor, so adjustments

to the voltage during the test are not required.

5.2.8

After 500 hours of applied bias (596 hours total), per-

form the insulation resistance measurements, as before.

5.2.9

Additional temperature/humidity/bias conditioning may

be performed after 500 hours of bias, sometimes up to 1000

hours or more. However, the 500 hours bias testing results

provide a minimum standard for reporting CAF testing

results when using this procedure.

5.2.10

Suspect CAF test failures may be checked to deter-

mine whether the connecting wire attach area is the low resis-

tance site rather than the daisy-chain area. This requires

cutting the trace near the daisy chain (destructive). After all

testing is completed, if the connecting wire attach area rather

than the daisy chain area is then found to be the low insula-

tion resistance site, then that test sample is no longer valid for

data analysis.

Number

2.6.25

Subject

Conductive Anodic Filament (CAF) Resistance Test: X-Y Axis

Date

02/21

Revision

IPC-TM-650

shall

Page

5.3 Data Handling and Analysis

5.3.1

Lognormal plots are recommended for plotting per-

cent of samples above an insulation resistance value, versus

insulation resistance. Use the log value of the insulation resis-

tance.

5.3.2

If lognormal plots are not used, a test circuit failure

be determined by more than a decade drop in insulation

resistance as a result of the applied bias. The baseline for the

decade drop

be the average insulation resistance at 96

hours for each coupon (A-1, A-2, etc.).

5.3.3

Test board nets with less than 10 megohms insulation

resistance (high resistance short) after the 96-hour stabiliza-

tion

be excluded, since these failures are due to poor

PTH hole quality or laminate capability.

5.3.4

The insulation resistance baseline (before bias condi-

tioning) value for a given daisy-chain net (same design spac-

ing)

be the average resistance of those un-shorted

daisy-chain nets on all test boards in the valid sample group

as measured after the 96-hours stabilization period.

5.3.5

The percent failure rate for a given sample group and

subsequent test condition is the percent of test boards that

show more than a decade drop in resistance compared with

the baseline value for daisy-chain nets with the same design

spacing.

5.3.6

For a given sample lot, there may be binomial failure

distributions where assignable causes exist along with differ-

ent levels of capability.

5.4 Visual Examination

After completion of the test, the

test boards

be removed from the environmental cham-

ber and examined at 10X magnification for evidence of sur-

face insulation resistance failure (i.e., discoloration, corrosion),

handling or processing defects other than CAF.

5.4.1 Assignable Cause

Where an assignable cause of

low insulation resistance can be properly attributed to a han-

dling or processing defect other than CAF (i.e., contamination

on the insulating surface of the board, scratches, cracks, or

other obvious damage affecting the insulation resistance

between the conductors), then such a value should be

excluded.

5.4.2 CAF Microsections

Since CAF filaments form along

the interface between resin and the woven reinforcement,

these filaments can be very small and easily disrupted by a

relatively low current flow or other causes. Microsectioning to

observe CAF filaments can be a tedious process with a low

success rate.

5.5 Reporting Results

5.5.1

The percent failure rate at 500 hours for each spacing

in sections A and B are the results of interest. Generally PWB

processing has the greatest impact on reduced CAF resis-

tance at smaller plated-through hole-to-plated-through hole

(PTH-PTH) spacings, while the laminate material has the

greatest impact at larger PTH-PTH spacings. However, the

laminate material used can also affect the extent of fracturing

and copper wicking near a PTH.

5.5.2

There are several additional factors that can affect

CAF resistance. See APPENDIX A for the list of PCB manu-

facturing parameters that may affect CAF resistance and that

should be documented.

6 Notes

6.1 Definitions [Only those terms not already included in IPC-

T-50.]

The growth of metallic conductive salt filaments by means

of an electrochemical migration process involving the

transport of conductive chemistries across a nonmetallic

substrate under the influence of an applied electric field,

thus producing Conductive Anodic Filaments.

The growth of conductive metal filaments across or

through a dielectric material in the presence of moisture

and under the influence of voltage bias.

This is a multi-functional surface finish wherein the electro-

less nickel layer is capped with a thin layer of immersion

gold. It is applicable to soldering, aluminum wire bonding,

press fit connections and as a contact surface. The

immersion gold protects the underlying nickel from

oxidation/passivation over its intended life.

An underwriters Laboratories Inc. (UL) requirement value

of laminate materials as determined by the results of tests

performed by UL.

Number

2.6.25

Subject

Conductive Anodic Filament (CAF) Resistance Test: X-Y Axis

Date

02/21

Revision

IPC-TM-650

shall

Conductive

Anodic

Filament

(CAF)

Formation:

Electrochemical

Migration

(ECM):

shall

Electroless

Nickel

Immersion

Gold

(ENIG):

Maximum

Operating

Temperature

(MOT):

Page

A surface finish for fine pitch featured PCBs that are often

assembled using surface mount components (SMCs). The

OSP surface finish provides very flat/co-planar land areas

for the placement and attachment of SMC devices.

This phrase alludes to the manufacturing of a bare printed

circuit board that is not populated (assembled) with any

discrete components.

6.2 Reference Documents

Electrochemical Migration: Electrically Induced

Failures in Printed Wiring Assemblies

Electrochemical Migration

Resistance Test (note: covers only surface electrochemical

migration)

Surface Insulation Resistance Handbook

Number

2.6.25

Subject

Conductive Anodic Filament (CAF) Resistance Test: X-Y Axis

Date

02/21

Revision

IPC-TM-650

—

Organic

Solderability

Preservative

(OSP):

Printed

Circuit

Board

Fabrication

(PCB

Fab):

IPC-TR-476

IPC-TM-650,

Method

2.6.14.1

IPC-9201

Page