IPC-TM-650 EN 2022 试验方法-- - 第755页
Failure T ype & Distance (between drilled hole walls, o r hole wall to plane edge). Examples: PTH-PTH, 11.0 mils, N elco 4000-11 PTH-Plane ( GND), 15.0 mils , FR406 (dic y-cu r ed) Current Limiting Resistor Value (de…
APPENDIX A
Additional CAF Resistance Factors Checklist
Test board part number and revision level.
Drilled Hole Size for each Hole-Hole and Hole-Plane spacing tested (also
recommend drilling feed rate, speed of rotation, chip loading data, backup
material type, etc.).
Desmear & Cleaning Process (ex: permanganate, plasma).
Whether glass microetch was used (and if so, the controlling process
parameters).
Board finish type (HASL or specific OSP, immersion silver, immersion tin,
ENIG, etc.).
Laminate material type that was used (manufacturer and material name or
number).
Woven Glass Manufacturer (silane treatment application).
Type of soldermask (if used).
PCB Fab manufacturer and facility.
Method of separating test board from working panel.
Number of circuit layers in test board.
Copper thickness in plated through holes in test board.
Dielectric Thickness and Construction (same construction throughout is
recommended for CAF testing). Examples:
Core 2/2 3.0 mils thick 1 ply 1080, Prepreg 1 ply 1080
Core 1/1 4.3 mils thick 1-106/1-1080, Prepreg 1-106/1-1080
Core H/H 5.0 mils thick 1-2113, Prepreg 1-2113
Failure Location (with examples)
Glass-Resin Boundary
Migration Between Glass Fibers
Migration Between Fiber Bundles
Void within Fiber Bundle
Incomplete Wetting Against Fiber
Hollow Fiber (report glass cloth supplier name, name of fiber source)
Test Interruptions:
Cause (example: power interruption)
Length of Interruption
Test Re-Start Parameters
Frequency of Measurement. Examples:
24 Hours
20 Minutes
6 Minutes
Time of Failure: Examples
200 Hours (hollow fiber)
300 Hours (void within fiber bundle)
21 Hours (migration between fiber bundles)
Number
2.6.25
Subject
Conductive Anodic Filament (CAF) Resistance Test: X-Y Axis
Date
02/21
Revision
C
IPC-TM-650
Document
for
every
CAF
resistance
test
the
several
additional
factors
that
can
affect
C4F
resistance.
These
critical
factors
include:
Parameters
Comments
Page
10
of
11
Failure Type & Distance (between drilled hole walls, or hole wall to plane
edge). Examples:
PTH-PTH, 11.0 mils, Nelco 4000-11
PTH-Plane (GND), 15.0 mils, FR406 (dicy-cured)
Current Limiting Resistor Value (default is 1.0 meg-ohm or 10
6
ohms)
Assembly Process Simulation: Examples
No Bake, No Preconditioning
Bake (specify), No Preconditioning
Bake (specify), 3X @ 260 °C Preconditioning (specify profile)
Bake (specify), 6X @ 260 °C Preconditioning (specify profile)
Bake (specify), 6X @ 230 °C Preconditioning (specify profile)
Bake (specify), 5X @ 245 °C Preconditioning (specify profile)
CAF Test Parameters: Examples
15 Vdc, 50 °C, 80% RH, drilled hole wall to hole wall spacings
100 Vdc, 65 °C, 87% RH, drilled hole wall to hole wall spacings
10 Vdc, 65 °C, 85% RH, drilled hole wall to hole wall spacings
Material(s) Tested: Examples
FR406 (dicy-cured)
Nelco 4000-11
Reporting Dates: Examples
Date Tested: August 2006
Date CAF Test Coupon Manufactured: February 2006
Number
2.6.25
Subject
Conductive Anodic Filament (CAF) Resistance Test: X-Y Axis
Date
02/21
Revision
C
IPC-TM-650
Parameters
Comments
Page
11
of
11
1 Scope
These methods determine the physical endurance
of representative coupons of printed boards to a series of high
temperature excursions from ambient. The temperature
excursions cause thermo-mechanical fatigue of the electrical
interconnect structures.
The test coupon is resistance heated by passing DC current
through the coupon to bring the temperature of the copper to
a designated temperature. Switching the current on and off
creates thermal cycles between room temperature and the
designated temperature within the sample. The laminate and
surrounding materials are heated to different extents depend-
ing on the thermal conductivity of the materials. The thermal
cycling can accelerate latent interconnect anomalies to failure.
The number of cycles achieved permits a quantitative assess-
ment of the performance.
1.1 Method A Description
Method A uses a coupon with
two or more independent electrical nets. The designation for
these nets is either a power net (P) or a sense net (S). Each
electrical net consists of plated barrels and conductors (inter-
nal and external). DC current is passed through one electrical
net to heat the coupon to a designated temperature. When
the electrical net is at the designated temperature, the DC
current is turned off and cooling fans are turned on to cool the
coupons to ambient temperature. One heating and cooling
sequence represents a thermal cycle. Thermal cycling is con-
tinued to either a set number of cycles or a failure. Tempera-
ture coefficient of resistance (TCR) is estimated by proprietary
algorithms.
A failure is based on a percentage change in the bulk resis-
tance of the coupon at the designated test temperature. The
percentage change is measured independently for each elec-
trical net being tested. When the percentage change is
exceeded, the test is stopped for the coupon.
1.2 Method B Description
Method B uses a coupon with
one electrical net. The net consists of via structures con-
nected by external and/or internal circuit lines in a daisy chain.
DC current is passed through the electrical net to heat the
coupon to a designated temperature. When the electrical net
is at the designated temperature, the DC current is turned off
and a cooling fan is turned on to cool the coupons to ambient
temperature. One heating and cooling sequence represents a
thermal cycle. Thermal cycling is continued to either a set
number of cycles or a failure. Temperature coefficient of resis-
tance (TCR) is measured.
A failure is based on a percentage change in the bulk resis-
tance of the coupon at the designated test temperature. The
percentage change is measured independently for each elec-
trical net being tested. When the percentage change is
exceeded, the test is stopped for the coupon.
2 Applicable Documents
2.1 IPC
1
Method Development Packet
Test Methods Manual
2
2.1.1 Microsectioning
2.5.35 Capacitance of Printed Board Substrates After
Exposure to Assembly, Rework, and/or Reliability
Tests. (At the time of publication of this test method,
2.5.35 is in development.)
2.6.27 Thermal Stress, Convection Reflow Assembly
Simulation
3 Test Specimens
A typical daisy chain test coupon for
each method is shown in Figure 3-1 and Figure 3-2.
1. www.ipc.org
2. Current and revised IPC Test Methods are available on the IPC Web site (www.ipc.org/html/testmethods.htm)
3000 Lakeside Drive, Suite 309S
Bannockburn, IL 60015-1249
IPC-TM-650
TEST METHODS MANUAL
Number
2.6.26
Subject
DC Current Induced Thermal Cycling Test
Date
5/14
Revision
A
Originating Task Group
PTV Reliability Test Methods (6-10c)
Association
Connecting
Electronics
Industries
IPC-MDP-650
IPC-TM-650
Material
/n
this
Test
Methods
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