Test_Flow_for_Advanced_Packages_WhitePaper_1115.pdf - 第5页
ADV ANCED P ACKAGE TEST FLOW 5 all the assembly is completed and the device is in its final form, the device is sent for FT . During FT , the device is tested for performance using the mini m um datasheet specifications …
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Test Flow for Advanced Packages (2.5D/SLIM/3D)
The process of building a “chip” can be viewed as a fan-out process, where the die is
attached to a substrate or interposer, which provides electrical connectivity from the enclosed die to
the outside world. The substrate converts the die’s fine pitch and small pads to a pad size and pitch
that can be easily assembled on a printed circuit board. In the case of a multichip module, the
substrate or interposer also provides electrical connectivity to other dies on the interposer or
substrate. Typically the substrates are electrically tested by the substrate manufacturer and only
known good substrates (KGSu) are shipped to the OSAT. In the case of a 2.5D interposer, since the
interposers are shipped to the OSAT as full thickness wafers, top to bottom connections on the
interposer can only be checked after the wafer is thinned and TSVs are exposed. In the case of 3D
chips, known good die (KGD) are stacked and bonded over each other. However, in the case of SiPs,
either KGD or known good devices are populated onto the substrate or interposer.
Figure 1: Traditional Test Insertion Points for Semiconductor Test
As shown in Figure 1, the standard test insertion points during traditional semiconductor test
at an OSAT are Wafer Sort (WS), Final Test (FT) and, in some cases, System Level Test (SLT). At
Wafer Sort, OSAT’s use automated test equipment (ATE) and automated probers that handle full
thickness wafers (~800 µm). Here devices are tested for functionality rather than performance. After
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all the assembly is completed and the device is in its final form, the device is sent for FT. During FT,
the device is tested for performance using the minimum datasheet specifications as the lower limit.
Devices that are targeted for specific applications in a reference design environment undergo SLT.
Improving Interposer Yield using Redundancy - Eliminating the Need to Test
The interposer wafer may consist of two or three metal layers, usually built using mature
process node technologies such as 90nm or 65nm. These proven technologies provide highly reliable
connections between dies and from die to the TSVs. The potential risk in connectivity can occur if
the interposer has non-uniform TSVs. For example, if a single TSV were used to make a connection
between the front side metal and the backside C4, and if this TSV’s height were 10 µm shorter than
the rest, no connection would result. However, adding multiple (one or more) redundant TSVs for
each C4 connection, as shown in Figure 2, significantly increases the yield to the point where testing
may not be necessary.
If a customer deems interposer testing necessary, they add daisy chain structures at certain
strategic locations. Testing is usually done from the C4 side, where the pad diameter is 80 µm and
the pitch is 120 to 150 µm, allowing for simple cantilever probe cards for test. During interposer test,
if an open is detected in any of these test structures, the interposer die is marked as bad (unusable).
Figure 2: Redundant TSVs to C4 connection
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Test Challenges with Advanced Packaging Technologies
When the goal of an advanced package is to have high performance at a lower power budget,
the test requirements get pushed from “sub-speed testing” to “at speed testing.” Now the device has
to be tested for performance at the speed at which it is designed to operate and not a fraction of its
operational speed. This offers new challenges – such as making electrical contact, high-speed
performance of the probe card, high-current consumption of the device (at probe), bare-die handling
and heat dissipation (see Figure 3).
Figure 3: New Assembly Techniques provide New Test Challenges
To maintain signal integrity at high speeds, large sacrificial pads are replaced with small pads
that attach to the micro-bumps. The number of pins that make contact with the probe card can be in
the range of 20,000. With a 5-gm force per probe needle, the probe card core can experience over
100 Kg of force, making it susceptible to bending and reducing planarity. Furthermore, device
operating currents could well be in the 10’s of amperes range, limiting the choice of needle
technology. Running the device at speed, while checking for performance, creates large amounts of
heat. To prevent thermal runaway, the die is tested at subzero temperatures requiring special gaskets
to prevent condensation and water/ice buildup on the tester-prober interface.