ISM6636A&B_Rev1.10解密.pdf - 第17页

17 Innovision Semiconductor Preliminary Datas heet ISM6636 A/B Rev1.10 01/2023 Switching frequency The switching frequency of the ISM6636A/B is depend on the VOUT.For the VO UT of 5V, the SW frequency is normally 1. 875M…

Innovision Semiconductor

Preliminary Datasheet

ISM6636A/B

Rev1.10 01/2023

user register Vout_high_byte[0] and user

Over-current protection (OCP) and over-

voltage protection (OVP) are both engaged

during soft start period to protect

ISM6636A/B from being damaged during

short circuit and over-voltage, respectively.

Table 2 SoftStopEnable and SoftDisable Register

Description

To achieve the best system accuracy, it is

recommended that the output voltage is

programmed by using the user registers

with appropriate codes. The output voltage

when programmed using the codes should

not be more than +/-20% of the preset

default voltage value.

Figure 1 Timing Diagram of Soft Start

Startup with Prebias

The ISM6636A/B supports smooth pre-bias

startup. When the output is pre-charged

with some voltage, both high side and low

side FETs are tri-stated. Once the internal

soft-start (SS) signal exceeds the output

voltage sensed at the VOS pin, the on-time

control is enabled which allows the turn-on

of the high side FET and followed by the

turn-on of the low side FET. The power

good circuit is not active until the first on

pulse is initiated.

Shutdown

The ISM6636A/B supports two ways of

shutting down.

1. Hard stop by Enable pin. When the

enable signal is forced low, both high side

and low side gate drivers are turned off

immediately. The internal softstart (SS)

signal is pulled down immediately as well.

The output voltage is discharged by the

load it is carrying.

2. Soft-stop by I2C register. When the user

the user register bit SoftDisable is also set

to 1, the internal SS signal ramps down

following the same rate as it rises during

the initial softstart. Both gate drivers are

disabled only when the SS voltage reaches

0. The output voltage ramps down to 0 at

the rate set by the SS.

The ISM6636A/B does not support on the

fly change of SoftDisable bit when the

device is actively switching. For

applications that require soft-stop, this bit

must be set to 1. When EN pin is high, the

SoftStopEnable bit must be toggled to soft

start and/or soft stop the device. The

default shutdown mode for ISM6636A/B is

hard stop by EN pin.

SoftStop

Enable

SoftDisable

Description

0x14[2]

0x1C[3]

Use EN pin. Soft

Stop is disabled

Same as above

Soft Stop is

active regardless

EN pin voltage

Innovision Semiconductor

Preliminary Datasheet

ISM6636A/B

Rev1.10 01/2023

Switching frequency

The switching frequency of the

ISM6636A/B is depend on the VOUT.For

the VOUT of 5V, the SW frequency is

normally 1.875MHz when the VOS is

connected to the VOUT.

Enable

The EN pin is used to enable or disable

ISM6636A/B. It has a precise threshold that

is monitored internally by the UVLO circuit.

If the EN pin is floating, the internal resistor

pulls it down to prevent the device from

inadvertently switching.

The EN pin can also be used to achieve

accurate input voltage UVLO. The input of

the EN pin is the PVIN voltage obtained by

a set of resistance dividers, REN1 and

REN2 (Figure 2). The user can program the

UVLO threshold voltage by selecting

different ratios. This will help to shut down

the device when the PVIN is below the

required voltage level.

The EN pin can be connected directly to the

PVIN without any external resistance

dividers. This is a useful feature when no

enable signals are available.

The EN pin can also be used to monitor

other power supplies for a particular power

sequencing arrangement (Figure 2).

Figure 2 Single Supply Configuration

Figure 3 External Bias Supply

Over-current protection (OCP)

The ISM6636A/B is designed with over

current protection function (OCP). The

current information is sensed through the

low side FET Rds_ON.The on-die OCP

provides accurate overcurrent protection

without the use of additional external sense

resistor. Since the current sense is done

on-die, the noise impact to the system is

minimized.

The OCP threshold is internally

temperature compensated, making it

almost constant at different ambient

temperatures.

Innovision Semiconductor

Preliminary Datasheet

ISM6636A/B

Rev1.10 01/2023

If the ISM6636A/B detects over-current

condition for 16 consecutive cycles and PG

signal is low, or the VOS falls below to 50%

of set value, the low side FET remains on

until the current falls to 0A, and then

ISM6636A/B enters hiccup mode (Figure 4).

Both the high side and low side FETs

remain off during the fault protection mode.

After the blanking time, ISM6636A/B will

attempt to restart. If the over-current fault is

still present, the above operation repeats

itself. The ISM6636A/B will remain in

hiccup mode until the over-current fault is

cleared.

Figure 4 OCP in Hiccup Mode

Over-voltage protection (OVP)

The ISM6636A/B is designed with over

voltage protection function (OVP). OVP is

provided by sensing the voltage at the VOS

pin. When the VOS exceeds the output

OVP threshold with greater than OVP delay

(usually 7μs), a fault condition will occur.

The OVP threshold is determined by the

user register bit OV_Threshold definition

(see Table 4 below).

Bits

Name/Description

0x17

[1:0]

OV_SET:

00:105% of VOUT

01:110% of VOUT

10:115% of VOUT

11:120% of VOUT(default)

Table 4 OV_Threshold Register Description

When OVP happens, the high side FET is

turned off immediately and the PG pin is

pulled low. The low side FET is fully turned

on until the inductor current reaches zero.

Once zero crossing is reached, both high

side and low side FETs are tri-stated. When

the output voltage is discharged below the

reference voltage level, PWM starts

switching again. When the output voltage

falls below the 102.5% of reference level,

PG re-asserts.

If OV_Response register is set to 0, the

high side FET remains off until reset by

cycling VCC or EN signals. The voltage at

the VOS pin falling below the output OVP

threshold does not turn on the high side

FET, but it turns off the low side FET to

prevent the negative current from building

up.

Bits

Name/Description

0x1A

[0]

OV_Response:

0：latch off

1：no latch off

Table 5 OV_Response Register Description

Over-temperature protection

(OTP)

When the on-die temperature falls within

the operating range, the device will

automatically restart. The OTP threshold