技术资料.pdf - 第27页
27 Figure 17 . 34950A 64 - c hann el d igi tal I /O
26
34950A 64 bit I/O
Digital input/output characteristics
Number of channels
Eight 8 bits. Input or output, non-isolated
V
in
0 V – 5 V
1
V
out
1.65 V – 5 V
1,2
I
out
(max) 24 mA
2
Frequency (max)
10 MHz
3
I
load
(max)
400 mA
t
rise
+ t
fall
(typ)
6 ns
5
Handshake lines
V
in
0 V – 5 V
V
out
1.65 V – 5 V
2,4
I
out
(max)
24 mA
2
Frequency (max)
10 MHz
Counter function characteristics
Max frequency
10 MHz (max) 50% duty cycle
V
in
0 V to 5 V
Min rise/fall time
5 µsec
Totalizer function characteristics
Maximum count
2
32
-1 (4,294,967,296)
Maximum input frequency
10 MHz (max), rising or falling edge, programmable
V
in
0 V – 5 V
Gate input
0 V – 5 V
Maximum input frequency
5 µsec
System clock generator characteristics
Frequency
20 MHz – 10 Hz, configurable divide by-n 24-bits, programmable on/off
V
out
1.65 V – 5 V
2
I
out
(max)
24 mA
2
Accuracy
100 ppm
Note:
1. Configurable by 8-bit channel
2. Lower current drive at lower voltages
3. From memory with handshaking
4. Configurable by bank
5. 5V, 50 pF load
28
34951A 4-Channel Isolated D/A Converter with
Waveform Memory
This module has four independent, isolated channels that output DC voltage up to ± 16 V or DC current
up to ± 20 mA. The gain and offset can be adjusted on-the-fly.
Each channel can be controlled manually or use the onboard memory to download a waveform. The 500k
of memory is global and can store up to 32 waveforms. Any waveform can be dynamically allocated
among one or more channels and output as a point-to-point arbitrary waveform generator at up to 200k
points/sec. You can use the standard since square or ramp wave shapes provided or define your own
wave shape using over 500k points and output to a device under test. There is also a single CLK that can
be divided down for each channel independently. The calibration command connects the D/A converters
to the internal DMM to be automatically calibrated. Connections to the module can be made via standard
50-pin Dsub, cables, or a detachable terminal block.
34951A 4 channel D/A
General specifications
Maximum update rate
200 kHz point-to-point
Monotonic
To 16 bits
Isolation
> 80 VDC/AC peak (chan-to-chassis or chan-to-chan)
Synchronization
Software commands or external trigger
Internal/external CLK accuracy
100 ppm
AC accuracy
Not specified
DC voltage
Amplitude
± 16 V up to 10 mA
Resolution
16 bits = 500µV
Amplitude accuracy
± (0.05% + 3.0 mV) (90 days, Tcal ± 5 °C or Cal:MOD?: ± 5 °C)
Ripple and noise
< 2 mVrms, 20 Hz to 250 kHz into 10 kΩ load
Settling time
40 µS (-full scale to +full scale step, single-channel, to rated accuracy)
Output impedance
< 1 Ω with the load sensed
DC current
Range
± 20 mA
Resolution
16-bit = 630 nA
Accuracy
± (0.09% + 5.0 μA) (90 days, Tcal ± 5 °C or Cal:MOD?: ± 5 °C)
Ripple and noise
< 2 μArms, 20 Hz to 250 kHz into 250 Ω
Compliance voltage
± 12 V
Maximum open circuit voltage
< ± 22 V
Trigger input
Input level
TTL compatible (3.3 V logic, 5 V tolerant)
Slope
Rising or falling, selectable
Pulse width
> 100 ns
Input impedance
> 10 kΩ, DC coupled