IPC-4556 印制板化学镍钯浸金(ENEPIG)规范ENG.pdf - 第84页
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SUMMARY
The electroless Ni, electroless Pd, and immersion Au (ENEPIG) surface finish is capturing the attention of both the struc-
tural and electronics soldering communities as a means to enhance the solderability of common base materials for a range
of applications. Solderability testing has illustrated the robustness of this finish after simulated storage aging using the
Battelle Class 2 environment. For the various ENEPIG finishes in this study, the excellent performance was sensitive to sup-
plier but not to the thickness of the Pd layer. Only a slight decrease in wetting rate was observed after exposure to the
Battelle Class 2 conditions. Auger electron spectroscopy (AES) identified two possible sources of the reduced wetting rate:
(a) Pd diffusion to the Au surface and its oxidation and (b) the small build-up of carbon compounds that are attracted to the
Au layer.
REFERENCES
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2. W. H. Abbott, ‘‘The Development and Performance Characteristics of Mixed Flowing Gas Test Environment,’’ IEEE
Transactions, Vol. 11, No. 1, March 1988.
3. A. Jackson, I. Artaki, and P.Vianco, ‘‘Manufacturing Feasibility of Several Lead Free Solders for Electronic Assembly,’’
Proc. 7
t
h Inter. SAMPE Electronics Conf. (Parsippany, NJ; June 21, 1994), p. 381.
4. I. Artaki, A. Jackson, and P. Vianco, ‘‘Fine Pitch Surface Mount Assembly with Lead-Free, Low Residue Solder Paste,’’
Proc. Surface Mount Inter., (San Jose, CA Aug. 28, 1994), p. 495.
5. P. Vianco, J. Rejent, I. Artaki, and U. Ray, ‘‘An Evaluation of Prototype Circuit Boards Assembled with a Sn-Ag-Bi Sol-
der,’’ Proc. IPC Works ’99 (IPC, Northbrook, IL; 1999), p. S-03-3-1.
6. P. Vianco and A. Claghorn, ‘‘Effect of Substrate Preheating on Solderability Performance as a Guideline for Assembly
Development - Part I: Baseline Analysis,’’ Soldering and Surface Mount Technology No. 24 (1996) p. 12.
7. R. J. K. Wassink, Soldering Electronics, (Ayr, Scotland: Electrochemical Publications Limited, 1984) p. 235.
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ANSI/IPC-T-50 Terms and Definitions for
Interconnecting and Packaging Electronic Circuits
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