Samsung（三星）-KLM8G1GEAC-B001.pdf - 第27页

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IF THERE IS ANY OTHER OPERATION TO IMPLEMENT IN ADDITION TO SPECIFICATION
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datasheet
e·MMC
Rev. 1.0
KLMxGxGEAC-B001
SAMSUNG CONFIDENTIAL
7.0 AC PARAMETER
7.1 Timing Parameter
[Table 35] Timing Parameter
NOTE:
1) Normal Initialization Time without partition setting
2) Initialization Time after partition setting, refer to INI_TIMEOUT_AP in 6.4 EXT_CSD register
3) Timeout values are measured based on Samsung's test pattern
4) Under severe user cases, EXCEPTION_EVENT occurs and Timeout values have possibility to increase
7.2 Previous Bus Timing Parameters for DDR52 are defined by JEDEC standard
Timing Paramter Max. Value Unit
Initialization Time (tINIT)
Normal
1)
1s
After partition setting
2)
3s
Read Timeout 100 ms
Write Timeout 350 ms
Erase Timeout 20 ms
Force Erase Timeout 3 min
Secure Erase Timeout 8s
Secure Trim step1 Timeout 5s
Secure Trim step2 Timeout 3s
Trim Timeout 600 ms
Partition Switching Timeout (after Init) 100 us
Power Off Notification (Short) Timeout 100 ms
Power Off Notification (Long) Timeout 600 ms
- 26 -
IF THERE IS ANY OTHER OPERATION TO IMPLEMENT IN ADDITION TO SPECIFICATION
IN THE DATASHEET OR JEDEC STANDARD, PLEASE CONTACT EACH BRANCH OFFICE OR
HEADQUARTERS OF SAMSUNG ELECTRONICS.
datasheet
e·MMC
Rev. 1.0
KLMxGxGEAC-B001
SAMSUNG CONFIDENTIAL
7.3 Bus Timing Specification in HS200 mode
7.3.1 HS200 Clock Timing
Host CLK Timing in HS200 mode shall conform to the timing specified in Figure 7 and Table 37. CLK input shall satisfy the clock timing over all possible
operation and environment conditions.CLK input parameters should be measured while CMD and DAT lines are stable high or low, as close as possible
to the Device. The maximum frequency of HS200 is 200MHz. Hosts can use any frequency up to the maximum that HS200 mode allows.
Figure 7. HS200 Clock signal timing
NOTE : 1. V
IH
denote V
IH
(min.) and V
IL
denotes V
IL
(max.).
2. V
T
=0.975V - Clock Threshold, indicates clock reference point for timing measurements.
[Table 36] HS200 Clock signal timing
7.3.2 HS200 Device Input Timing
Figure 8. HS200 Device input timing
NOTE : 1. t
ISU
and t
IH
are measured at V
IL
(max.) and V
IH
(min.).
2. V
IH
denote V
IH
(min.) and V
IL
denotes V
IL
(max.).
[Table 37] HS200 Device input timing
symbol Min. Max. Unit Remark
t
PERIOD
5 - ns 200MHz (Max.), between rising edges
t
TLH
, t
THL
0.2 * t
PERIOD
ns
t
TLH
, t
THL
< 1ns (max.) at 200MHz,
C
BGA
= 12pF, The absolute maximum value of
t
TLH
, t
THL
is 10ns regatdless of clock frequency
Duty Cycle 30 70 %
Symbol Min. Max. Unit Remark
t
ISU
1.40 - ns
5pF≤C
BGA
≤ 12 pF
t
IH
0.8 ns
5pF≤C
BGA
≤12pF
t
TLH
t
THL
t
PERIOD
V
IH
V
T
V
IL
VCCQ
VSS
CLOCK
INPUT
VALID
WINDOW
V
IL
V
IH
t
IH
t
ISU
V
IL
V
IH
VCCQ
VSS
CMD.DAT[7-0]
INPUT
t
PERIOD
CLOCK
INPUT
V
T
VCCQ
VSS
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IF THERE IS ANY OTHER OPERATION TO IMPLEMENT IN ADDITION TO SPECIFICATION
IN THE DATASHEET OR JEDEC STANDARD, PLEASE CONTACT EACH BRANCH OFFICE OR
HEADQUARTERS OF SAMSUNG ELECTRONICS.
datasheet
e·MMC
Rev. 1.0
KLMxGxGEAC-B001
SAMSUNG CONFIDENTIAL
7.3.3 HS200 Device Output Timing
t
PH
parameter is defined to allow device output delay to be longer than t
PERIOD
. After initialization, the t
PH
may have random phase relation to the clock.
The Host is responsible to find the optimal sampling point for the Device outputs, while switching to the HS200 mode.
Figure 9 and Figure 38 define Device output timing. While setting the sampling point of data, a long term drift, which mainly depends on temperature
drift, should be considered. The temperature drift is expressed by Δ
TPH
. Output valid data window (t
VW
) is available regardless of the drift (Δ
TPH
) but
position of data window varies by the drift, as describes in Figure 10 .
Figure 9. HS200 Device output timing
NOTE: V
OH
denotes V
OH
(min.) and V
OL
denotes V
OL
(max.).
[Table 38] Output timing
NOTE: Unit Interval (UI) is one bit nominal time. For example, UI=5ns at 200MHz.
Figure 10. Δ
TPH
consideration
Symbol Min. Max. Unit Remark
tPH 0 2 UI
Device output momentary phase from CLK input to CMD or DAT lines output.
Does not include a long term temperature drift.
Δ
TPH
-350
(ΔT=-20 deg.C)
+1550
(ΔT=90 deg.C)
ps
Delay variation due to temperature change after tuning.
Total allowable shift of output valid window (T
VW
) from last system Tuning
procedure
Δ
TPH
is 2600ps for ΔT from -25 deg.C to 125 deg.C during operation.
t
VW
0.575 - UI
t
VW
=2.88ns at 200MHz
Using test circuit in Figure 13 including skew among CMD and DAT lines
created by the Device.
Host path may add Signal Integrity induced noise, skews, etc. Expected T
VW
at
Host input is larger than 0.475UI.