Samsung（三星）-KLM8G1GEAC-B001.pdf - 第31页

- 30 - IF THERE IS ANY OTHER OPERATION TO IMPLEMENT IN ADDITION TO SPECIFICATION IN THE DATASHEET OR JEDEC STANDARD, PLEASE CONTACT EACH BRANCH OFFICE OR HEADQUARTERS OF SAMSUNG ELECTRONICS. datasheet e·MMC Rev. 1.0 KLMx…

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- 29 -
IF THERE IS ANY OTHER OPERATION TO IMPLEMENT IN ADDITION TO SPECIFICATION
IN THE DATASHEET OR JEDEC STANDARD, PLEASE CONTACT EACH BRANCH OFFICE OR
HEADQUARTERS OF SAMSUNG ELECTRONICS.
datasheet
e·MMC
Rev. 1.0
KLMxGxGEAC-B001
SAMSUNG CONFIDENTIAL
8.0 DC PARAMETER
8.1 Active Power Consumption during operation
[Table 42] Active Power Consumption during operation
* Power Measurement conditions: Bus configuration =x8 @200MHz
* The measurement for max RMS current is the average RMS current consumption over a period of 100ms.
8.2 Standby Power Consumption in auto power saving mode and standby state.
[Table 43] Standby Power Consumption in auto power saving mode and standby state
NOTE:
Power Measurement conditions: Bus configuration =x8, No CLK
*Typical value is measured at Vcc=3.3V, TA=25°C. Not 100% tested.
8.3 Sleep Power Consumption in Sleep State
[Table 44] Sleep Power Consumption in Sleep State
NOTE:
Power Measurement conditions: Bus configuration =x8, No CLK
1) In auto power saving mode, NAND power is alive.
2) In sleep mode, NAND power can be switched off. If NAND power is alive, it is same with the value in standby state.
8.4 Supply Voltage
[Table 45] Supply voltage
Density NAND Type CTRL NAND Unit
8 GB 64Gb x 1
150
80
mA
16 GB 64Gb x 2 130
32 GB 64Gb x 4
230
64 GB 64Gb x 8
Density NAND Type
CTRL NAND
Unit
25C(Typ) 85C 25C(Typ) 85C
8 GB 64Gb x 1
120 400
40 85
uA
16 GB 64Gb x 2 50 135
32 GB 64Gb x 4 70 235
64 GB 64Gb x 8 130 435
Density NAND Type
CTRL
NAND Unit
25C(Typ) 85C
8 GB 64Gb x 1
120 400
0
1)
uA
16 GB 64Gb x 2
32 GB 64Gb x 4
64 GB 64Gb x 8
Item Min Max Unit
V
DD
(V
CCQ
) 1.70 (2.7) 1.95 (3.6) V
V
DDF
(V
CC
) 2.7 3.6 V
Vss -0.5 0.5 V
- 30 -
IF THERE IS ANY OTHER OPERATION TO IMPLEMENT IN ADDITION TO SPECIFICATION
IN THE DATASHEET OR JEDEC STANDARD, PLEASE CONTACT EACH BRANCH OFFICE OR
HEADQUARTERS OF SAMSUNG ELECTRONICS.
datasheet
e·MMC
Rev. 1.0
KLMxGxGEAC-B001
SAMSUNG CONFIDENTIAL
8.5 Bus Signal Line Load
The total capacitance C
L
of each line of the e·MMC bus is the sum of the bus master capacitance C
HOST
, the bus capacitance C
BUS
itself and the capac-
itance C
DEVICE
of the e·MMC connected to this line:
C
L
= C
HOST
+ C
BUS
+ C
DEVICE
The sum of the host and bus capacitances should be under 20pF.
[Table 46] Bus SIgnal Line Load
Parameter Symbol Min Typ. Max Unit Remark
Pull-up resistance for CMD R
CMD
4.7 100 KOhm to prevent bus floating
Pull-up resistance for DAT0-DAT7 R
DAT
10 100 KOhm to prevent bus floating
Internal pull up resistance DAT1-DAT7
R
int
10 150 KOhm
to prevent unconnected lines
floating
Single e·MMC capacitance C
BGA
12 pF
Maximum signal line inductance 16 nH f
PP
<= 52 MHz
- 31 -
IF THERE IS ANY OTHER OPERATION TO IMPLEMENT IN ADDITION TO SPECIFICATION
IN THE DATASHEET OR JEDEC STANDARD, PLEASE CONTACT EACH BRANCH OFFICE OR
HEADQUARTERS OF SAMSUNG ELECTRONICS.
datasheet
e·MMC
Rev. 1.0
KLMxGxGEAC-B001
SAMSUNG CONFIDENTIAL
A. e·MMC Connection Guide
This connection guide is an example for customers to adopt e·MMC more easily
This appendix is just guideline for e·MMC connection. This value and schematic can be changed depending on the system environment.
Coupling capacitor should be connected with VDD and VSS as close as possible.
VDDI Capacitor is min 0.1uF
Impedance on CLK match is needed.
0Ω ~47Ω is available for resistance on CLK line according to a system environment.
If host does not have a plan to use H/W reset, it is not needed to put 50KΩ pull-up resistance on H/W reset line.
SAMSUNG recommends user separate VDD and VDDF power.
A.1 x8 support Host connection Guide
A.2 x4 support Host connection Guide
e·MMC
VDDF
C
2.0uF
C
0.1uF
Host Controller
VDD
VDD
VDD
CMD
CLK
DAT0
DAT1
DAT2
DAT3
DAT4
DAT5
DAT6
DAT7
R
50k
R
50k
R
50k
R
50k
R
50k
R
50k
R
50k
R
50k
R
10k
DAT0
DAT1
DAT2
DAT3
DAT4
DAT5
DAT6
DAT7
CMD
CLK
VDDF
VDD
VSS
VDDI
RSTN
H/W RESET
R
50k
C
0.2uF
C
2.0uF
C
0.2uF
e·MMC
VDDF
C
0.2uF
C
2.0uF
C
0.1uF
Host Controller
VDD
VDD
VDD
CMD
CLK
DAT0
DAT1
DAT2
DAT3
R
50k
R
50k
R
50k
R
50k
R
10k
DAT0
DAT1
DAT2
DAT3
DAT4
DAT5
DAT6
DAT7
CMD
CLK
VDDF
VDD
VSS
VDDI
RSTN
H/W RESET
R
50k
C
0.2uF
C
2.0uF