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Micromachines 2026 , 17 , 592 10 of 34 Structurally , the probe head consists of two ceramic layers with guiding holes for the electrical probes, separated by a metallic ﬂexure structure, as illustrated in Figure 3 . Bas…

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non-normal, particularly as the number of optimization problems increases. They advocate

for more rigorous statistical approaches including performance proﬁles and data proﬁles.

Performance proﬁles [

] measure the fraction of problems solved within a given

performance ratio relative to the best solver. Data proﬁles [

] extend this concept by

plotting the fraction of problems solved as a function of the number of function evaluations,

providing insight into convergence speed and robustness. These proﬁle-based methods are

particularly appropriate for optimization algorithm comparison, as they account for the

full distribution of performance rather than relying on potentially misleading averages.

3. Methodology

3.1. Eclipse Dynamic System Architecture

To address the severe spatial constraints associated with conventional lateral edge

coupling in high-density wafer-level environments, the Eclipse Dynamic system employs

lensed ﬁbers and 3D-printed micro-lenses [

] to redirect the optical signal from horizontal

propagation to vertical access. This conﬁguration enables dense wafer-level probing while

remaining compatible with standard prober geometries and integrated electro-optical

test operation.

Figure 2 presents the system-level architecture of the Eclipse Dynamic probe card

during wafer-level testing. The tester provides both the electrical test program and the

optical test program. The optical path comprises a source/modulation stage and a detection

stage connected to the integrated FAU in the probe head, while the mechanical alignment

loop is closed through the controller and the piezoelectric drive electronics. The FAU

is integrated into the probe head together with the electrical probes, such that optical

and electrical contact are established on the same wafer site during probing. Rather than

actuating individual ﬁbers independently, the system displaces the entire FAU as a single

rigid body in the X–Y plane, with differential actuation used for tilt compensation. This

architecture eliminates the need for external optical positioning stages and enables compact,

high-throughput wafer-level electro-optical testing.

Electrical Test

Testing program

Optical Test

Testing program

Optical

Modulator

Photoelectric

Converter

Optical Alignment Algorithm

Controller

Piezo Power Supplier

Piezo Voltage Boost

Probe Head

Align loop

Fiber Array Unit

PCB

Tester

Piezo

Wafer

Probes

Figure 2. System-level block diagram of the automated wafer-level photonic testing platform, show-

ing the tester, controller, optical source/detection chain, piezoelectric drive electronics, integrated

probe head, and wafer under test.

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Structurally, the probe head consists of two ceramic layers with guiding holes for

the electrical probes, separated by a metallic ﬂexure structure, as illustrated in Figure 3.

Based on the patented mechanical architecture [

], this ﬂexure supports the integrated

FAU and is actuated by three piezoelectric elements: one actuator controls the X-axis, while

two parallel actuators (Y1 and Y2) control the Y-axis. Differential driving of Y1 and Y2

provides the rotational tilt compensation required for precise optical alignment, whereas

the vertical Z-axis approach is handled by the prober chuck rather than by the integrated

piezoelectric stage.

Probes

FAU

(a) (b)

Figure 3. Eclipse Dynamic Probe Head architecture. (a) Complete probe head assembly showing

electrical probes and FAU integration. (b) Internal ﬂexure mechanism showing the piezoelectric

actuators (X, Y1, Y2) used for nanometric alignment, with their respective positions marked in

blue [8].

The embedded FAU is a conﬁgurable interface rather than a ﬁxed-format optical array.

In particular, the number of ﬁbers and the ﬁber pitch are selected according to the PIC

under test, including the number of optical channels, the spacing between input/output

ports, and the pitch of the access couplers or waveguides on the chip. Accordingly, the

FAU geometry is customized to match the DUT layout while remaining compatible with

the mechanical and electrical constraints of the integrated probe head. More generally,

the underlying probe-head concept supports multi-channel optical interfacing through an

optical distribution element comprising a plurality of waveguides aligned to the probe-

head structure by dedicated alignment features [

]. Because the input and output ﬁbers

are ﬁxed within one rigid FAU block, they are aligned simultaneously as a uniﬁed assembly

rather than sequentially.

The actuators are controlled through the probe card PCB, driven by the tester system.

The operating voltage range is 0–120 V, corresponding to a total displacement range of

m in the X–Y plane. Under typical operating conditions, the system achieves

positioning resolution better than 1 nm, enabling precise alignment to grating couplers

with typical mode-ﬁeld diameters of 10–15 µm.

Because the probe head is a highly compact integrated electro-optical environment,

embedding physical displacement sensors for closed-loop optical alignment would in-

troduce undesirable spatial and packaging complexity. Therefore, the system relies on

open-loop control. Although the complete hardware architecture and containment-element

kinematics have been deﬁned in foundational patents and prior literature [

], the

remainder of this study focuses speciﬁcally on the computational efﬁciency, reliability, and

optimization of the automated optical alignment algorithms.

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3.2. Experimental Characterization

3.2.1. Hysteresis Measurement

As described in Section 2, the piezoelectric actuators in the Eclipse Dynamic system

exhibit path-dependent hysteresis whose magnitude scales with the applied voltage range.

To quantify this behavior for the speciﬁc axes and operating conditions of this work, we

performed controlled voltage sweeps on the physical hardware while measuring displace-

ment with a high-resolution optical measurement system. A ceramic reference plate with

precision markers was mounted on the ﬂexure, and displacement was recorded as voltage

was increased and decreased in steps.

The experimental protocol reads as follows. Voltage was swept for each of the three

physical actuators (X, Y1, and Y2) from 0 V to each of six peak levels (20, 40, 60, 80, 100,

and 120 V) and returned to 0 V, with the resulting spatial displacement recorded at every

step. This protocol isolates how hysteresis error scales with the peak operating voltage.

The measured hysteresis loops representing the resulting spatial movement along

the X and Y axes are shown in Figure 4. Three characteristics are directly relevant to the

algorithm design. First, hysteresis is strongly voltage-dependent: at a peak drive of 100 V

the X-axis positioning error is approximately 3.5%, whereas extending to the full 120 V

operating range raises this to approximately 15%. Second, the forward path (increasing

voltage, solid lines) and return path (decreasing voltage, dashed lines) diverge substantially,

with the descending trajectory consistently underreaching the forward-path displacement

at equivalent drive levels. Third, restricting actuation to the 20–40 V range limits hysteresis

to 2–4%, indicating that algorithms operating via small, localized voltage increments will

inherently encounter fewer nonlinearity effects than those requiring wide-range excursions.

We additionally observed a slight non-orthogonality between the X and Y axes, attributed

to asymmetric Y1/Y2 actuator characteristics and their sequential rather than simultaneous

activation; this cross-coupling is accounted for in all alignment algorithm implementations.

0 20 40 60 80 100

X Voltage (V)

X Displacement ( m)

X-Axis Hysteresis

100V Max (up)

100V Max (down)

80V Max (up)

80V Max (down)

60V Max (up)

60V Max (down)

40V Max (up)

40V Max (down)

20V Max (up)

20V Max (down)

0 20 40 60 80 100

Y Voltage (V)

Y Displacement ( m)

Y-Axis Hysteresis

100V Max (up)

100V Max (down)

80V Max (up)

80V Max (down)

60V Max (up)

60V Max (down)

40V Max (up)

40V Max (down)

20V Max (up)

20V Max (down)

Figure 4. Measured hysteresis loops for Eclipse Dynamic system at different maximum voltages.

Hysteresis increases with voltage magnitude, reaching

∼

15% at 120 V operation. Solid lines show

forward path (increasing voltage), dashed lines show return path (decreasing voltage). Left: X-axis

behavior. Right: Y-axis behavior.

These measurements provided the voltage trajectory data used to identify the inverse

P-I calibration described in Section 2. The resulting reset-to-zero timing overhead is

captured in the hardware timing model of Section 3.3.4.

3.2.2. Optical Power Measurements

The experimental optical setup is conﬁgured to measure insertion loss continuously

during the active alignment process. The apparatus utilizes a continuous-wave laser source

coupled into the single-mode optical ﬁbers of the integrated probe head. Light is injected

https://doi.org/10.3390/mi17050592