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Micromachines 2026 , 17 , 592 3 of 34 This is a necessary evolution for high-volume scenarios: an integrated optical probe card can save precious seconds per die in alignment, which compounded over hundreds of dies yield…
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Keywords: Photonic Integrated Circuits; wafer-level testing; probe card; optical alignment;
piezoelectric actuation; Bayesian optimization; hysteresis compensation
1. Introduction
Wafer-level testing of photonic integrated circuits (PICs) has emerged as a critical
bottleneck in the silicon photonics manufacturing flow [
1
]. The convergence of opti-
cal and electronic components in PICs has revolutionized high-speed data transmission,
telecommunications, and sensing applications [
1
]. As PIC complexity grows exponentially,
driven by demands from data centers and 5G networks, wafer-level testing has become
increasingly critical to ensure device functionality and yield before expensive packaging
processes [2].
Unlike standard electronic ICs, PICs require simultaneous electrical and optical char-
acterization, presenting unique challenges for test equipment design. A fundamental
bottleneck in PIC wafer probing is achieving precise optical coupling between optical
fibers and on-chip waveguides, which demands alignment tolerances typically in the range
of 100 nm or better across six degrees of freedom [
3
,
4
]. Traditionally, these alignments
have been performed using external optical positioning systems, such as hexapods and
piezoelectric actuators mounted on prober peripheries, or by slow automated routines.
While functional in lab settings, these external setups significantly increase equipment cost,
footprint, and setup complexity, resulting in substantial test time per device [
4
]. With test-
ing already accounting for roughly 30% of the total manufacturing cost of a PIC device [
3
],
these external systems severely limit throughput and make parallel testing of multiple
devices challenging. This time and cost pressure is only growing as PIC volumes increase
and diverse optical I/O designs (grating couplers, edge couplers, etc.) proliferate.
The industry moving toward co-packaged optics (CPO) in high-performance comput-
ing and data centers further amplifies the challenge, as wafer-level optical testing must scale
to meet the throughput demands of potentially thousands of optical I/O per wafer [
1
,
3
]. In
CPO-enabled photonic engines, PIC dies with dramatically higher port counts need to be
tested rapidly to avoid becoming a production bottleneck [3].
Recent advances have fundamentally changed the architecture of PIC wafer test equip-
ment. On one front, there is a push toward integrated probe head solutions that combine
optical and electrical probing in a single apparatus, eliminating the need for separate
bulky aligners. One such design philosophy relies on passive, alignment-insensitive optical
coupling: the on-card optics are engineered so that the positional tolerances of the prober
chuck alone provide adequate coupling, effectively removing per-die active alignment
overhead and pushing throughput toward the electrical-probing limit [4–6].
Our work is based on the Technoprobe Eclipse Dynamic probe system, an alternative
approach which co-integrates a fiber array unit (FAU) and piezoelectric micro-positioners
directly into the probe card [
7
,
8
]. The FAU is mounted on a flexure mechanism and actuated
by three piezoelectric elements operating over a voltage range of 0–120 V, providing a
displacement range of 15
µ
m
×
15
µ
m alongside necessary tilt compensation. This enables
high-precision optical alignment through automated routines without the need for external
positioning equipment. Rather than relying on cumbersome, large, and slow external tools,
this design integrates the active alignment capability directly into a compact, dynamic probe
head, drastically reducing move-and-align times between dies. Integration of intelligent
control and monitoring frameworks [
9
] further enhances the capability of the system for
high-volume production environments. As a result, the typical active alignment time
(which once took on the order of tens of seconds per die) can be significantly reduced [
4
,
10
].
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This is a necessary evolution for high-volume scenarios: an integrated optical probe card
can save precious seconds per die in alignment, which compounded over hundreds of dies
yields substantial throughput gains [6,10,11].
Equally important, integrating the optical aligners into the probe hardware enables
parallel multi-channel testing. For instance, the Eclipse Dynamic (and similar systems)
can couple many fiber channels at once, leveraging parallel optical tests to further boost
throughput. Probe-card-based architectures that co-integrate optical and electrical inter-
faces are already enabling this parallelism [
5
,
12
], and recent fully automated wafer-level
systems demonstrate the viability of high-throughput multi-site electro-optical characteri-
zation [10].
Another key aspect of our solution is its cost-effective control strategy. High-
performance aligners often employ closed-loop feedback (using interferometric sensors
or strain gauges) to achieve nanometric precision and to counteract piezo hysteresis and
drift. Piezoelectric actuators inherently exhibit this hysteresis behavior, where displacement
depends not only on the applied voltage but also on the voltage history [
13
]. Because this
non-linearity is particularly pronounced at higher voltages, it can significantly impact
alignment accuracy and speed. However, implementing closed-loop control to mitigate this
in a dense multi-fiber probe head would add considerable complexity and cost. Instead,
the Eclipse Dynamic system exploits advanced open-loop control with algorithmic com-
pensation for these actuator nonlinearities. Furthermore, because each measurement point
requires time for actuator movement and signal settling, the choice of alignment algorithm
and operating speed regime plays a crucial role in determining overall testing throughput.
However, modern modeling techniques for piezoelectric actuators have made it feasi-
ble to achieve accuracies of a few nanometers without physical feedback sensors. Hysteresis
operators like the Preisach and Prandtl–Ishlinskii (P-I) model can be mathematically in-
verted for feedforward linearization of piezo stages [
14
,
15
]. Recent research has improved
upon these classical models to address rate-dependent and asymmetric hysteresis, using
modified P-I operators or even data-driven approaches (e.g., sparse and machine-learning-
based hysteresis models) for greater accuracy [
16
,
17
]. By leveraging such techniques, our
piezo actuators in the probe head are software-linearized, enabling repeatable sub-micron
alignments in open-loop. This avoids the need for embedded nano-position encoders
on each axis, thereby simplifying the probe hardware and enhancing robustness in a
production environment.
In this work, we present a comprehensive study of alignment optimization tech-
niques. We evaluate seven different alignment algorithms through both experimental
measurements and simulated data generated from experimental scans. Each algorithm was
evaluated across eight distinct on-wafer die locations (spanning multiple reticle positions)
directly on the Eclipse Dynamic hardware. Our analysis considers both high-speed (HS)
and low-speed (LS) operating regimes, as well as the impact of piezoelectric hysteresis on
alignment performance. Following best practices for algorithm comparison [
18
], we employ
data profile analysis rather than simple averaging to account for the non-normal distribu-
tion of convergence steps, particularly as the number of optimization problems increases.
The key contributions of this work can thus be listed as:
•
Comprehensive experimental characterization of seven alignment algorithms on eight
real wafer-level PIC coupling scenarios;
•
Simulation framework for generating synthetic alignment scenarios with controllable
hysteresis effects;
• Statistical analysis using data profiles for rigorous algorithm comparison;
•
Comparative performance evaluation across high-speed and low-speed operating
conditions;
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•
Practical guidelines for algorithm selection based on operating regime and hystere-
sis conditions;
•
Systematic hyperparameter optimization of Bayesian algorithms between experimen-
tal and simulation phases.
While the individual search algorithms utilized in this study are established numerical
methods, the core contribution of this work is their rigorous, system-level benchmarking
within the strict hardware constraints of industrial PIC testing. By evaluating these algo-
rithms under diverse operational extremes, we provide actionable guidelines for production
deployment. These algorithms are particularly vital for emerging coupling approaches,
such as 3D-printed edge couplers or micro-optics [
19
], where device-to-device spatial
variations are larger and demand highly robust dynamic active alignment.
The remainder of this paper is organized as follows: Section 2 reviews related work in
PIC testing and alignment optimization. Section 3 describes the Eclipse Dynamic system
and details the alignment algorithms under investigation. Section 4 presents experimental
and simulation results with data profile analysis. Section 5 discusses the comparative
performance and provides recommendations. Finally, Section 6 concludes the paper and
outlines future work.
2. Background
2.1. Wafer-Level Photonic Testing and Integrated Probe Head Architectures
Wafer-level testing of PICs has attracted growing attention, driven by the need to
validate optical performance at scale before costly packaging steps [
3
,
4
]. A central challenge
is related to achieving reliable, repeatable fiber-to-chip optical coupling across hundreds
of dies per wafer, each requiring sub-micron positional accuracy in multiple degrees of
freedom [
3
]. Early test setups relied on ad-hoc laboratory configurations in which skilled
operators manually aligned individual optical fibers using bench-top micro-positioners,
resulting in test times on the order of minutes per die and making high-volume charac-
terization practically infeasible [
4
]. The broader silicon photonics community has since
worked toward automated, reproducible measurement flows that integrate optical probing
with standard wafer probers [2,4].
A key architectural trend is the consolidation of optical and electrical probing into a
unified probe head compatible with conventional wafer probers, eliminating the need for
separate, bulky fiber positioning equipments. Two distinct philosophies have emerged.
The first relies on passive, alignment-insensitive optical coupling: by carefully engineering
the beam characteristics of the on-card optics, the positional tolerances of the prober chuck
become sufficient for adequate coupling without any per-die active correction, effectively
removing per-die alignment overhead and pushing throughput toward the electrical-
probing limit [
4
,
5
]. The second philosophy, adopted in the present work, retains active
micro-positioning of the FAU within the probe head using compact piezoelectric actuators,
allowing fine coupling optimization on each die and accommodating device-to-device
variation at the cost of a short, software-driven alignment routine per die [
7
,
8
]. Both
approaches represent a clear departure from external hexapod or gantry aligners attached
to the prober periphery, which added equipment cost, floor-space overhead, and limited
the degree of test parallelism achievable.
Probe-card-based solutions capable of parallel multi-channel measurements have been
demonstrated for a range of PIC types. Petrini et al. integrated a fiber-array probe with an
electrical card to enable simultaneous multi-channel characterization of photonic filters
without external positioning equipment [
5
]. Wu et al. demonstrated a butt-coupling probe
card with on-board polarization control, allowing polarization-sensitive PICs to be tested at
wafer scale without any separate fiber aligner [
12
]. Recent work by Jansen et al. presented
https://doi.org/10.3390/mi17050592