multifunction-rio-user-manual.pdf - 第39页
Chapter 2 Hardware Overview of the NI 78x x © National Instruments Corporation 2-21 Multifunction Reconfigurabl e I/O User Manual R TSI T rigger Bus The NI 78 xx can send and receive triggers through th e RTSI trigger bu…
Chapter 2 Hardware Overview of the NI 78xx
Multifunction Reconfigurable I/O User Manual 2-20 ni.com
The SHC68-68-RDIO was designed specifically for R Series devices and is
the NI-recommended cable for digital applications. If you are using the
SH68-C68-S cable, however, please note the following considerations.
The SH68-C68-S shielded cable contains 34 twisted pairs of conductors. To
maximize the digital I/O available on the NI 78xx, some of the DIO lines
are twisted with power or ground and some DIO lines are twisted with other
DIO lines. To obtain maximum signal integrity, place edge-sensitive or
high-frequency digital signals on the DIO lines that are paired with power
or ground. Because the DIO lines that are twisted with other DIO lines can
couple noise onto each other, use these lines for static signals or
non-edge-sensitive, low-frequency digital signals. Examples of
high-frequency or edge-sensitive signals include clock, trigger, pulse-width
modulation (PWM), encoder, and counter signals. Examples of static
signals or non-edge-sensitive, low-frequency signals include LEDs,
switches, and relays. Table 2-4 summarizes these guidelines.
Table 2-4. DIO Signal Guidelines for the NI 78xx
Device Digital Lines
SH68-C68-S
Shielded Cable
Signal Pairing
Recommended Types
of Digital Signals
NI 781x DIO<0..27> DIO line paired
with power
or ground
All types—high-frequency or
low-frequency signals,
edge-sensitive or
non-edge-sensitive signals
DIO<28..39> DIO line paired
with another
DIO line
Static signals or
non-edge-sensitive,
low-frequency signals
NI 783x,
NI 784x,
NI 785x
Connector 0, DIO<0..7>;
Connector 1, DIO<0..27>;
Connector 2, DIO<0..27>
DIO line paired
with power
or ground
All types—high-frequency or
low-frequency signals,
edge-sensitive or
non-edge-sensitive signals
Connector 0, DIO<8..15>;
Connector 1, DIO<28..39>;
Connector 2, DIO<28..39>
DIO line paired
with another
DIO line
Static signals or
non-edge-sensitive,
low-frequency signals
Chapter 2 Hardware Overview of the NI 78xx
© National Instruments Corporation 2-21 Multifunction Reconfigurable I/O User Manual
RTSI Trigger Bus
The NI 78xx can send and receive triggers through the RTSI trigger bus.
The RTSI bus provides eight shared trigger lines that connect to all the
devices on the bus. In PXI, the trigger lines are shared between all the PXI
slots in a bus segment. In PCI, the RTSI bus is implemented through a
ribbon cable connected to the RTSI connector on each device that needs to
access the RTSI bus.
You can use the RTSI trigger lines to synchronize the NI 78xx to any other
device that supports RTSI triggers. On the PCI-781x/783x and
PCIe-784x/785x, the RTSI trigger lines are labeled RTSI/RTSI<0..6> and
RTSI/RTSI7. On the PXI-78xx, the RTSI trigger lines are labeled
PXI/PXI_Trig<0..7>. In addition, the PXI-78xx can use the PXI star trigger
line to send or receive triggers from a device plugged into Slot 2 of the PXI
chassis. The PXI star trigger line on the PXI-78xx is PXI/PXI_Star.
The NI 78xx can configure each RTSI trigger line either as an input or an
output signal. Because each trigger line on the RTSI bus is connected in
parallel to all the other RTSI devices on the bus, only one device
should drive a particular RTSI trigger line at a time. For example, if
one PXI-78xx is configured to send out a trigger pulse on PXI/PXI_Trig0,
the remaining devices on that PXI bus segment must have PXI/PXI_Trig0
configured as an input.
Caution Do not drive the same RTSI trigger bus line with the NI 78xx and another device
simultaneously. Such signal driving can damage both devices. NI is not liable for any
damage resulting from such signal driving.
For more information on using and configuring triggers, select Help»
Search the LabVIEW Help in LabVIEW to view the LabVIEW Help.
Refer to the PXI Hardware Specification Revision 2.1 and PXI Software
Specification Revision 2.1 at
www.pxisa.org for more information about
PXI triggers.
PXI Local Bus (PXI-781x /783x Only)
The PXI-781x/783x can communicate with other PXI devices using the
PXI local bus. The PXI local bus is a daisy-chained bus that connects each
PXI peripheral slot with its adjacent peripheral slot on either side. For
example, the right local bus lines from a PXI peripheral slot connect to the
left local bus lines of the adjacent slot on the right. Each local bus is 13 lines
wide. All of these lines connect to the FPGA on the PXI-781x/783x. The
Chapter 2 Hardware Overview of the NI 78xx
Multifunction Reconfigurable I/O User Manual 2-22 ni.com
PXI local bus right lines on the PXI-781x/783x are PXI/PXI_Lbr<0..12>.
The PXI local bus left lines on the PXI-781x/783x are
PXI/PXI_Lbl<0..12>.
The PXI-781x/783x can configure each PXI local bus line either as an input
or an output signal. Only one device can drive the same physical local bus
line at a time. For example, if the PXI-781x/783x is configured to drive a
signal on PXI/PXI_Lbr 0, the device in the slot immediately to the right
must have its PXI/PXI_Lbl 0 line configured as an input.
Caution Do not drive the same PXI local bus line with the PXI-781x/783x and another
device simultaneously. Such signal driving can damage both devices. NI is not liable for
any damage resulting from such signal driving.
The PXI-781x/783x local bus lines are only compatible with 3.3 V
signaling LVTTL and LVCMOS levels.
Caution Do not enable the local bus lines on an adjacent device if the device drives
anything other than 0–3.3V LVTTL signal levels on the PXI-781x/783x. Enabling the lines
in this way can damage the PXI-781x/783x. NI is not liable for any damage resulting from
enabling such lines.
The left local bus lines from the left peripheral slot of a PXI backplane
(Slot 2) are routed to the star trigger lines of up to 13 other peripheral slots
in a two-segment PXI system. This configuration provides a dedicated,
delay-matched trigger signal between the first peripheral slot and the
other peripheral slots for precise trigger timing signals. For example—as
shown in Figure 2-12—an PXI-781x/783x in Slot 2 can send an
independent trigger signal to each device plugged into Slots <3..15> using
the PXI/PXI_Lbl<0..12>. Each device receives its trigger signal on its own
dedicated star trigger line.
Caution Do not configure the NI 781x/783x and another device to drive the same physical
star trigger line simultaneously. Such signal driving can damage the NI 781x/783x and the
other device. NI is not liable for any damage resulting from such signal driving.