IPC-SM-782A-表面贴装焊盘图形设计标准.pdf.pdf - 第138页
Page Intentionally Left Blank IPC-SM-782 Subject Components with J Leads on Two Sides Date 8/93 Section 10.0 Revision P a g e2o f2
1.0 INTRODUCTION This section covers land patterns for
components with J leads on two sides. Each subsection con-
tains information in accordance with the following format:
1.0 Scope
2.0 Applicable Documents
3.0 General Component Description (Figure 1)
4.0 Component Dimensions (Figure 2)
5.0 Land Pattern Dimensions (Figure 3)
6.0 Tolerance and Solder Joint Analysis (Figure 4)
The following is the table of contents for this section:
Table of Contents
Section Component
10.1 SOJ
2.0 APPLICABLE DOCUMENTS
The following documents, of the issue in effect on the revision
date of this section, form a part of this specification to the
extent specified herein.
2.1 Electronic Industries Association (EIA)
1
JEDEC Publication 95 Registered and Standard Outlines for
Solid State and Related Products:
MO-077, issue ‘‘C,’’ dated 8/91
MO-065, issue ‘‘A,’’ dated 5/87
MO-063, issue ‘‘A,’’ dated 4/2/87
MO-061, issue ‘‘C,’’ date 8/91
EIA-PDP-100 Registered and Standard Mechanical Outlines
for Electronic Parts
EIA-481-A Taping of Surface Mount Components for Auto-
matic Placement
EIA-481-3 32 mm, 44 mm, and 56 mm Embossed Carrier
Taping of Surface Mount Components for Automated Han-
dling
2.2 Electronic Industries Association of Japan (EIAJ)
EIAJ-ED-7406
General Rules for the Preparation of Outline
Drawings of Integrated Circuits
2.3 International Electrotechnical Commission (IEC)
2
IEC 97 Grid Elements
3.0 General Information
3.1 General Component Description
This section pro-
vides the component and land pattern dimensions for small
outline integrated circuits with ‘‘J’’ leads (SOJ components).
Basic construction of the SOJ device is also covered. At the
end of the subsections are listings of the tolerances and tar-
get solder joint dimensions used to arrive at the land pattern
dimensions.
3.2 Packaging Components may be provided in tube or
tape packaging. Tape is preferred for best handling and high
volume applications. Bulk packaging is not acceptable
because of lead coplanarity requirements required for place-
ment and soldering. EIA-481 provides details on tape require-
ments.
1. Application for copies should be addressed to Global Engi-
neering Documents, 1990 M St. N.W., Washington, DC
20036.
2. Application for copies should be addressed to IEC, 3 rue
de Varembe, PO Box 131 - 1211 Geneva 20, Switzerland
IPC-SM-782
Surface Mount Design
and Land Pattern Standard
Date
8/93
Section
10.0
Revision Subject
Components with J Leads
on Two Sides
Page1of2
Page Intentionally Left Blank
IPC-SM-782
Subject
Components with J Leads on Two Sides
Date
8/93
Section
10.0
Revision
Page2of2
1.0 SCOPE
This subsection provides the component and land pattern
dimensions for small outline integrated circuits with ‘‘J’’ leads
(SOJ components). Basic construction of the SOJ device is
also covered. At the end of this subsection is a listing of the
tolerances and target solder joint dimensions used to arrive at
the land pattern dimensions.
2.0 APPLICABLE DOCUMENTS
See Section 10.0 for documents applicable to the subsec-
tions.
3.0 COMPONENT DESCRIPTIONS
The two-sided J lead family is a small outline family identified
by the dimension of the body size in inches. For example, the
SOJ/300 has a body size of 0.300 inches or 7.63 mm, the
SOJ/350 has a body size of 0.350 inches or 8.88 mm, the
SOJ/400 has a body size of 0.400 inches or 10.12 mm, and
the SOJ/450 has a body size of 0.450 inches or 11.38 mm.
Package lead counts range from 14 to 28 pins.
The small-outline ‘‘J’’ (SOJ) package has leads on two sides,
similar to a DIP. The lead configuration, like the letter J,
extends out the side of the package and bends under the
package forming a J bend. The point of contact of the lead to
the land
pattern is at the apex of the J bend and is the basis for the
span of the land pattern.
The leads must be coplanar within 0.1 mm. That is, when the
component is placed on a flat surface, no lead may be more
than 0.1 mm off the flat surface.
The SOJ package takes advantage of chips having parallel
address or data line layouts. For example, memory IC’s are
often used in multiples, and buss lines connect to the same
pin on each chip. Memory chips in SOJ packages can be
placed close to one another because of the parallel pin layout
and the use of ‘‘J’’ leads. With high capacity memory sys-
tems, the space savings can be significant.
3.1 Basic Construction See Figure 1. Basic construction
consists of a plastic body, and metallic ‘‘J’’ leads.
3.1.1 Termination Materials Leads must be solder-
coated with a tin/lead alloy. The solder should contain
between 58 to 68% lead. Solder may be applied to theleads
by hot dipping or by plating from solution. Plated solder termi-
nations should be subjected to post-plating reflow operation
to fuse the solder. The tin/lead finishshould be at least 0l.0075
mm [0.0003 in] thick.
3.1.2 Marking The SOIC family of parts is generally
marked with manufacturers part numbers, manufacturers
name or symbol, and a pin 1 indicator. Some parts may have
a pin 1 feature in the case shape instead of pin 1 marking.
Additional markings may include date code/manufacturing lot
and/or manufacturing location.
3.1.3 Carrier Package Format Components may be pro-
vided in tube or tape packaging. Tape is preferred for best
handling and high volume applications. Bulk packaging is not
acceptable because of lead coplanarity requirements required
for placement and soldering. EIA-481 provides details on tape
requirements.
3.1.4 Process Considerations J lead packages are nor-
mally processed using standard solder reflow processes.
Parts should be capable of withstanding ten cycles through a
standard reflow system operating at 215°C. Each cycle shall
consist of 60 seconds exposure at 215°C.
IPC-782-10-1-1
Figure 1 SOJ construction
IPC-SM-782
Surface Mount Design
and Land Pattern Standard
Date
5/96
Section
10.1
Revision
A
Subject
SOJ
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