MIL- STD-883F 2004 TEST METHOD STANDARD MICROCIRCUITS.pdf - 第635页

MIL-STD-883F METHOD 5006 20 November 1969 3 Step Test condit ion Pla ne 1 E Y 2 , X 1 , Z 1 , Y 1 2 F Y 2 , X 1 , Z 1 , Y 1 3 G Y 2 , X 1 , Z 1 , Y 1 4 H Y 2 , X 1 , Z 1 , Y 1 Elect ric al paramet er measur ements ( see …

100%1 / 708
MIL-STD-883F
METHOD 5006
20 November 1969
2
3.1.1 Thermal evaluation. This test shall be performed in accordance with method 1012, test condition B. With maximum
power applied, the complete temperature gradient of the active chip area shall be recorded. This data shall be analyzed to
determine that no areas of abnormally high operating temperatures are present as a result of improper design or processing.
The thermal resistance at the maximum operating temperature of the device shall be determined using test condition C or
method 1012.
3.1.2 Extended thermal shock
. The purpose of this testing is to establish the resistance of the device to thermal fatigue
effects. The device shall be subjected to a minimum of 100 cycles of thermal shock, in accordance with method 1011. This
test shall be conducted in the following sequence:
Step
Cycles Test condition
1 15 C
2 15 D
3 70 F
Parameter measurements (see 1.2) shall be made at the completion of 15, 30, 40, 70, and 100 cycles, and the number of
failures after each of these cycles shall be recorded.
3.1.2.1 Temperature cycling
. When specified in the applicable acquisition document, temperature cycling method 1010
may be substituted for the thermal shock test in 3.1.2. This test shall be conducted in the following sequence:
Step
Cycles Test condition
1 20 B
2 20 C
3 20 D
Parameter measurements (see 1.2) shall be made at the completion of each step, and the number of failures for each of
these steps shall be recorded.
3.1.3 Step-stress mechanical shock
. The purpose of this test is to establish the mechanical integrity of the device. The
device shall be subjected to mechanical shock in accordance with method 2002 and the following step-stress sequence:
Step
Test condition Plane No. of shocks
1 B Y
1
5
2 C Y
1
5
3 E Y
1
5
4 F Y
1
5
5 G Y
1
5
Electrical parameter measurements (see 1.2) shall be made after each step, and the number of failures incurred at each
step shall be recorded.
3.1.4 Step-stress constant acceleration
. The purpose of this testing is to establish the mechanical integrity of the device.
The device shall be subjected to a constant acceleration in accordance with method 2001 and the following step-stress
sequence:
MIL-STD-883F
METHOD 5006
20 November 1969
3
Step Test condition Plane
1 E Y
2
, X
1
, Z
1
, Y
1
2 F Y
2
, X
1
, Z
1
, Y
1
3 G Y
2
, X
1
, Z
1
, Y
1
4 H Y
2
, X
1
, Z
1
, Y
1
Electrical parameter measurements (see 1.2) shall be made after each plane, and the number of failures incurred shall be
recorded.
3.1.5 Step-stress operational life
. The purpose of this test is to establish the operational stress levels that will accelerate
predominant failure mechanisms so that meaningful failures can be generated in a relatively short period of time. The
results of the testing will also be utilized to evaluate the safety factors built into the device, to establish the safe constant
operational stress conditions, and to improve through corrective action(s) the reliability of the device. Electrical parameter
measurements shall be made after each stress level and the number of failures incurred in each step shall be recorded.
3.1.6 Constant high-stress operational life
. The purpose of this test is to induce meaningful operational failures in a
relatively short period of time and to compare the results of this testing with the results obtained from the step-stress
operational life. The stress level to be applied and intervals to intermediate electrical measurements shall be determined on
the basis of the results obtained in the step-stress tests (see 3.1.5). Electrical parameter measurements shall be made after
each specified time interval and the number of failures shall be recorded.
3.1.7 Step-stress storage life
. The purpose of this test is to establish the storage stress levels that will accelerate
predominant failure mechanisms so that meaningful failures can be generated in a relatively short period of time. The
storage temperatures and the step duration shall be established prior to initiation of testing. The results of the testing will be
utilized to evaluate the maximum limits of device resistance to failure at high temperature. Electrical parameter
measurements shall be made after each stress level and the number of failures incurred at each level shall be recorded.
3.2 Test condition B. Procedure for film and hybrid microcircuits
. Limit test shall be conducted in accordance with table I
and as described in 3.1.1 through 3.1.7 except that the specified test condition may be changed. When test condition or
stress levels are changed, they shall be established prior to the initiation of test. Failure analysis of all devices failing limit
tests shall be performed in accordance with method 5003, test condition B, unless otherwise specified in the applicable
acquisition document. Unless otherwise specified in the applicable acquisition document, limit testing in any test may be
discontinued after 50 percent of test sample has failed that specific test.
3.3 Test plan
. When required by the applicable acquisition document, the specific procedures for conducting limit testing
shall be submitted as a "Limit Test Plan" for approval by the acquiring activity prior to the initiation of testing. This plan shall
include the following as a minimum:
a. Activity responsible for performing the test.
b. Device types to be subjected to limit testing and criteria for their selection.
c. Failure criteria including electrical parameters to be measured.
d. Testing schedule.
e. Description of testing equipment.
f. Test condition if other than specified.
g. Data recording and reporting formats.
h. Data analysis procedures.
MIL-STD-883F
METHOD 5006
20 November 1969
4
4. SUMMARY. The following details shall be specified in the applicable acquisition document:
a. Test condition letter (see 3.1 and 3.2).
b. Test sequence and sample quantities if other than specified (see 3.1 and 3.2).
c. Failure analysis procedures and test condition, if other than specified (see 3.1 and 3.2).
d. For test condition B, the test conditions and stress levels, where applicable (see 3.2).
e. Percent failure for test termination, if other than specified (see 3.1 and 3.2).
f. Requirements for Limit Test Plan and data reporting (see 3.3).