IPC-SM-782A 表面安装设计和焊盘设计标准(带BGA).pdf - 第172页

Page Intentionally Left Blank IPC-SM-782 Subject Components with J Leads on Four Sides Date 8/93 Section 12.0 Revision P a g e2o f2 电子技术应用ｗｗｗ．ＣｈｉｎａＡＥＴ．ｃｏｍ

1.0 INTRODUCTION

This section covers land patterns for components with J leads

on four sides. Each subsection contains information in accor-

dance with the following format:

1.0 Scope

2.0 Applicable Documents

3.0 General Component Description (Figure 1)

4.0 Component Dimensions (Figure 2)

5.0 Land Pattern Dimensions (Figure 3)

6.0 Tolerance and Solder Joint Analysis (Figure 4)

The following is the table of contents for this section:

2.0 APPLICABLE DOCUMENTS

The following documents, of the issue in effect on the revision

date of this section, form a part of this specification to the

extent specified herein.

2.1 Electronic Industries Association (EIA)

EIA-481-A

Taping of Surface Mount Components for Auto-

matic Placement

EIA-481-3

32 mm, 44 mm, and 56 mm Embossed Carrier

Taping of Surface Mount Components for Automated Han-

dling

JEDEC Publication 95

Registered and Standard Outlines for

Solid State and Related Products

2.2 International Electrotechnical Commission (IEC)

IEC 97

Grid Elements

3.0 General Information

3.1 General Component Description

Leaded Chip Carri-

ers are either ceramic or plastic packages with terminations

which extend beyond the package outlines. These termina-

tions typically space the body of the package from the pack-

aging and interconnect structure for reasons of cleaning,

inspecting, or accommodating differences in thermal expan-

sion. The leads may be attached to the package body either

before or after chip attachment.

In plastic leaded chip carriers, the primary packaging distinc-

tion concerns the point in which a chip is incorporated into the

package. A pre-molded package is supplied as a leaded body

with an open cavity for chip attachment. A post-molded body

part typically has the chip attached to a lead frame with an

insulating plastic body molded around the assembly. It is sup-

plied from the manufacturer without apertures.

Leaded ceramic chip carriers may be similarly classified, but

with a difference in category. The distinction concerns the

point at which leads, if desired, are attached to the ceramic

body. A pre-leaded ceramic chip carrier is supplied with cop-

per or Kovar leads brazed to metallization integral with the

ceramic package. Typically, the package is supplied with an

open cavity for chip attach. A metal or ceramic lid is epoxied,

soldered, or attached with glass frit to provide a hermetic seal

around the chip. After these steps, the leaded assembly is

attached to the printed board.

A post-leaded ceramic chip carrier typically has leads sol-

dered to metallization on the ceramic package after chip

attachment. These leads may take the form of edge clips or

solder columns. Incorporation of leads into the assembly typi-

cally occurs immediately prior to board attachment.

High lead-end coplanarity in surface-mounted lead chip carri-

ers is an important factor in reliable solder attachment to the

printed board. Planarity may be measured from the lowest

three leads of a leaded package. Coplanarity of 0.1 mm

[0.004 in] maximum is recommended with 0.05 mm [0.002 in]

preferred.

1. Application for copies should be addressed to Global Engi-

neering Documents, 1990 M St. N.W., Washington, DC

20036.

2. Application for copes should be addressed to IEC, 3 rue

de Varembe, PO Box 131 - 1211 Geneva 20, Switzerland

IPC-SM-782

Surface Mount Design

and Land Pattern Standard

Date

8/93

Section

12.0

Revision Subject

Components with J Leads

on Four Sides

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Page Intentionally Left Blank

IPC-SM-782

Subject

Components with J Leads on Four Sides

Date

8/93

Section

12.0

Revision

Page2of2

电子技术应用　　　　　ｗｗｗ．ＣｈｉｎａＡＥＴ．ｃｏｍ

1.0 SCOPE

This subsection provides the component and land pattern

dimensions for plastic leaded chip carriers, square (PLCC

components) with J leads on four sides. Basic construction of

the PLCC device is also covered. At the end of this subsec-

tion is a listing of the tolerances and target solder joint dimen-

sions used to arrive at the land pattern dimensions.

2.0 APPLICABLE DOCUMENTS

See Section 12.0 for documents applicable

to the subsections.

2.1 Electronic Industries Association (EIA)

JEDEC Publication 95

Registered and Standard Outlines for

Solid State and Related Products, ‘‘Plastic Chip Carrier

(PLCC) Family, 1.27 mm [0.050 in] Lead Spacing, Square,’’

Outline MO-047, issue ‘‘B,’’ dated 11/88

Application for copies should be addressed to:

Global Engineering Documents

1990 M Street N.W.

Washington, DC

3.0 COMPONENT DESCRIPTIONS

Plastic leaded chip carriers are employed where a hermetic

seal is not required. Other constraints include limited tempera-

ture range (typically 0°C or 70°C) and nominal environmental

protection. As with plastic DIPs, they have the advantage of

low cost as compared to ceramic packages.

3.1.1 Pre-molded Plastic Chip Carriers

The pre-molded

plastic chip carrier was designed to be connected to the P&I

substrate by means of a socket. Spring pressure on both

sides of the package is intended to constrain movement as

well as allow for substrate warpage as high as 0.5%. Solder

attach to the P&I substrate is also possible. The design is also

intended to make use of silicone encapsulant technology for

chip coverage and protection.

3.1.2 Post-molded Plastic Chip Carriers

The post-

molded plastic leaded chip carrier is composed of a compos-

ite metal/dielectric assembly that includes a conductor lead

frame and a molded insulating body. Compared to the pre-

molded package which has an aperture for mounting micro-

electronic components, the post-molded package comes

complete with no apertures. In both types of plastic chip car-

riers, all necessary plating operations are performed by the

package manufacturer to eliminate tinning or plating by the

user.

The Joint Device Engineering Council (JEDEC) defines the

Type A Leaded Chip Carrier as a plastic package with leads

wrapped down and around the body on all four sides. This

package can be either directly mounted to a printed wiring

board or used with a socket. It is available with 28, 44, 52, 68,

84, 100, or 124 leads. This family is based on 1.27 mm [0.050

in] lead pitch. The original mechanical outline drawing of this

package was defined based on a premolded package. How-

ever, actual construction is not specified and the package

could be of post-molded construction.

Post-molded packages which have J-lead configuration and

are

JEDC standard MO-047, are available in 20-, 28-, 44-, 52-,

68-, 84-, 100- and 124-lead counts with the

same spacing.

3.1.3 Marking

All parts shall be marked with a part number

and ‘‘Pin 1’’ location. ‘‘Pin 1’’ location may be molded into the

plastic body.

3.1.4 Carrier Package Format

Bulk rods, 24 mm tape/

8–12 mm pitch is preferred for best handling. Tube carriers

are also used.

3.1.5 Resistance to Soldering

Parts should be capable of

withstanding ten cycles through a standard reflow system

operating at 215°C. Each cycle shall consist of 60 seconds

exposure at 215°C. Parts must also be capable of withstand-

ing a minimum of 10 seconds immersion in molten solder at

260°C.

IPC-782-12-1-1

Figure 1 PLCC (Square)

IPC-SM-782

Surface Mount Design

and Land Pattern Standard

Date

5/96

Section

12.1

Revision

Subject

PLCC (Square)

Page1of4

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