IPC-SM-782A 表面安装设计和焊盘设计标准(带BGA).pdf - 第37页

Spacing requirements are usually the inverse of the toler - ances shown for conductors in T able 3–9. For additional information see IPC-D-310, Artwork Generation and Mea- surement T echniques. 3.6.4.2 Conductor Width an…

zero clearance devices. Via holes may be located under-

neath zero clearance surface mount packages in full surface

mount assemblies that will not be wave soldered. See Fig-

ure 3–26.

3.6.3.4 Vias as Test Points

Via holes are used to con-

nect surface mounted component lands to conductor layers.

They may also be used as test targets for bed-of-nails type

probes and/or rework ports. Via holes may be tented if they

are not required for node testing or rework. When a via is

used as a test point it is required that the location of a test

land be deﬁned. See Section 5.0.

3.6.4 Standard Fabrication Allowances

Manufacturing

tolerances or Standard Fabrication Allowances (SFA) exist

in all PB fabrication shops. Virtually every registration or

alignment operation that is performed has some potential

for misregistration. There are approximately 42 basic steps

in fabricating a multilayer PB, several of which involve

operations that require precision in location. They are as

follows: artwork generation, artwork tooling hole locations,

core material tooling hole size, inner layer image printing

operation, laminating ﬁxture tooling pin locations, material

shrinkage during lamination, drill tooling pin location, drill

x/y table tolerances, drill spindle tolerances, drill wander,

outer layer imaging, to name a few. The SFA considers all

of the tolerances of all the steps mentioned above. If all of

the equipment in a fabrication shop is old and worn the

SFA could be as high as 0.3 mm, whereas, a manufacturer

with new, precise equipment may have an SFA of 0.2 mm.

An industry average SFA of 0.4 mm may be used. The tol-

erance varies according to the printed board maximum

diagonal dimension and must be included in the land size

calculations. The fabricator should be consulted prior to

beginning a design to determine his SFA. With this num-

ber, the designer can proceed accordingly, preventing toler-

ances from stacking up and creating yield and/or produc-

tion problems. (See IPC-2221.)

3.6.4.1 Manufacturing Characteristics

Figure 3–27

shows the various characteristics of conductor geometry.

End product drawings and speciﬁcations should specify

only minimums for conductor width and spacing. Tolerance

with plating of ±0.03 mm [±0.001 in] can be achieved

under special conditions. Artwork allowances that should

be incorporated into a design are shown in Table 3–8.

IPC-782-3-21

Figure 3-21 Surface routing geometries

SURFACE ROUTING GEOMETRIES

DETAILS OF THIS GEOMETRY:

Conductors and clearances may be 0.15 mm

Requires liquid photoimageable soldermask

100% Grid based test node accessibility from either side

0.8 mm

Square Via

0.6 X 2.0 mm

Component land

IPC-3-22

Figure 3–22 Conductor routing capability test pattern

2 Channel 2 Channel 3 Channel 3 Channel 4 Channel 5 Channel

IPC-SM-782A December 1999

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Spacing requirements are usually the inverse of the toler-

ances shown for conductors in Table 3–9. For additional

information see IPC-D-310, Artwork Generation and Mea-

surement Techniques.

3.6.4.2 Conductor Width and Spacing Tolerances

The

presentation in Table 3–9 represents process tolerances that

can be expected with normal processing. (Speciﬁc process

IPC-782-3-23

Figure 3–23 Routing channels under SOIC land pattern with 28 pins

49 Routing Channels

0.6mm Square lands

0.25mm Routing Grid

0.125mm Conductors/Clearances

Routing

Channels

35 Routing Channels

Routing

Channels

▼

16mm

10mm

▼

15mm

9.5mm

▼

0.8mm Round lands

0.3mm Routing Grid

0.15mm Conductors/Clearances

IPC-782-3-24

Figure 3–24 Land pattern to via relationships

Typical land

Inside layer connection

0.5 mm [0.020 inch]

diameter

Two 0.2 mm [0.008]

wide Conductors

Three 0.15 mm [0.006 inch]

wide Conductors between holes

▼

Square land

0.50mm

[0.020] min

Chip Components and Feed Through Via Holes

0.50mm

[0.020] min

Good Design

Poor Design

Feed through lands flush against contact area

▼

Too close

to contact

area

December 1999 IPC-SM-782A

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tolerances should be discussed with the board manufac-

turer.) The tolerances are based on copper thickness up to

and including one ounce copper. For each ounce of addi-

tional copper, an additional 0.03 mm [0.001 in] variation

per conductor edge can be expected.

3.6.4.3 Conductive Pattern Feature Location Tolerance

The presentation in Table 3–10 is for the tolerance to be

applied to the nominal dimension chosen for the location of

the lands, connector contacts and conductors in relation

tothe datums. This tolerance includes tolerances for master

pattern accuracy, material movement, layer registration and

ﬁxturing.

3.6.4.4 Annular Ring Control

The annular ring is

deﬁned as the amount of land that is remaining after a hole

is drilled through it. With high density SMT designs, main-

taining minimum annular requirements has emerged as one

of the most difficult parts of multilayer PB fabrication in

terms of producibility. Perfect registration will maximize

the annular ring all around the drilled hole. Using a 0.8 mm

[0.030 in] land with a 0.5 mm [0.020 in] drill will result in

a 0.15 mm [0.006 in] annular ring under perfect registra-

tion conditions. If misregistration of 0.15 mm [0.006 in]

occurs in any direction, the result will be a 0.3 mm [0.010

in] annular ring on one side of the pad, and no annular ring

on the other side. If misregistration is greater than 0.15 mm

[0.006 in], i.e., 0.2 mm [0.008 in], then the drill will actu-

ally break out of the land. If the breakout is in the direc-

tion where the conductor connects to the land, the drill will

effectively disconnect the conductor from the land. The net

IPC-782-3-25

Figure 3–25 Examples of via positioning concepts

Side 2

Vias

Side 1

Vias

Side 1

Vias

Side 2

Vias

Chip component

PLCC

SOIC

IPC-782-3-26

Figure 3–26 Vias under components

Caution

Solder

Characteristic

Solder

Migration

▼

Wave Solder

▼

IPC-SM-782A December 1999

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