IPC-SM-782A 表面安装设计和焊盘设计标准(带BGA).pdf - 第8页
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13.1 DIP
14.0 COMPONENTS WITH BALL GRID ARRAY
CONTACTS
14.1 Plastic Ball Grid Array
14.2 1.27 mm Pitch Rectangular PBGA JEDEC
MS-028
Figures
Figure 1–1 Electrical assembly types.................................. 3
Figure 3–1 Examples of typical package styles and
package descriptive designators....................... 9
Figure 3–2 Lead-form (or terminal-shape) examples........ 10
Figure 3–3 Profile tolerancing examples ........................... 11
Figure 3–4 Example of C1206 capacitor dimensioning
for optimum solder fillet conditions ................. 12
Figure 3–5 Profile dimensioning of a gullwing
leaded SOIC.................................................... 13
Figure 3–6 Pitch for multiple-leaded components............. 15
Figure 3–7 Simplified electronic development
organization..................................................... 20
Figure 3–8 Recommended minimum land-to-land
clearances....................................................... 21
Figure 3–9 Component orientation for wave solder
applications...................................................... 21
Figure 3–10 Alignment of similar components.................... 22
Figure 3–11 Local/global fiducials....................................... 23
Figure 3–12 Panel/global fiducials....................................... 23
Figure 3–13 Fiducial types for vision systems .................... 24
Figure 3–14 Fiducial clearance requirements ..................... 24
Figure 3–15 Fiducial locations on a printed circuit board ... 25
Figure 3–16 Packaging and geometries.............................. 25
Figure 3–17 Surface mount conductor widths/
clearances vs. routing grids ............................ 26
Figure 3–18 Section view of multilayer board with
vias on 1.0 mm [0.040 in] centers .................. 26
Figure 3–19 Narrowed conductor........................................ 27
Figure 3–20 Conductor routing............................................ 27
Figure 3–21 Surface routing geometries............................. 28
Figure 3–22 Conductor routing capability test pattern ........ 28
Figure 3–23 Routing channels under SOIC land
pattern with 28 pins......................................... 29
Figure 3–24 Land pattern to via relationships..................... 29
Figure 3–25 Examples of via positioning concepts............. 30
Figure 3–26 Vias under components .................................. 30
Figure 3–27 Conductor characteristics................................ 31
Figure 3–28 Examples of modified landscapes .................. 32
Figure 3–29
Typical copper glass laminate panel............... 33
Figure 3–30
Conductor clearance for V-groove scoring ..... 34
Figure 3–31
Breakaway (routed pattern)............................. 35
Figure 3–32
Routed slots .................................................... 35
Figure 3–33
Gang solder mask window.............................. 36
Figure 3–34
Pocket solder mask windows.......................... 36
Figure 4–1 Component temperature limits........................ 37
Figure 4–2 General description of process validation
contact pattern and interconnect..................... 39
Figure 4–3 Photo image of IPC-A-49 test board for
primary side..................................................... 39
Figure 4–4 Flat ribbon, ‘‘L,’’ and gullwing lead joint
description....................................................... 40
Figure 4–5 Round or flattened (coined) lead joint
description....................................................... 40
Figure 4–6 ‘‘J’’ lead joint description ................................. 41
Figure 4–7 Rectangular or square end components......... 41
Figure 4–8 Cylindrical end cap terminations—joint
illustration ........................................................ 42
Figure 4–9 Bottom only terminations................................. 42
Figure 4–10 Leadless chip carriers with castellated
terminations—joint description........................ 43
Figure 4–11 Butt joint description........................................ 43
Figure 4–12 Thermal cycle excursion rate.......................... 44
Figure 5–1 Test via grid concepts ..................................... 47
Figure 5–2 General relationship between test contact
size and test probe misses ............................. 49
Figure 5–3 Test probe feature distance from
component....................................................... 50
Figure 7–1 Typical process flow for underside
attachment type 2c (simple) surface mount
technology....................................................... 54
Figure 7–2 Typical process flow for full surface
mount type 1b and 2b surface mount
technology....................................................... 54
Figure 7–3 Typical process flow for mixed technology
type 2c (complex) surface mount
technology....................................................... 55
Figure 7–4 In-line placement equipment........................... 55
Figure 7–5 Simultaneous placement equipment............... 55
Figure 7–6 Sequential placement equipment.................... 56
Figure 7–7 Sequential/Simultaneous placement
equipment........................................................ 56
Tables
Table 3–1 Terminal Position Prefixes.................................... 8
Table 3–2 Package-Outline-Style Codes.............................. 8
Table 3–3 Lead-Form (or Terminal-Shape) Suffixes........... 11
Table 3–4 Tolerance Analysis Elements for Chip Devices
Table 3–5 RLP Numbers..................................................... 17
Table 3–6 Worst-Case Environments and Appropriate
Equivalent Accelerated Testing .......................... 19
Table 3–7 Component Stand Off ........................................ 23
Table 3–8 Typical Values to Be Added or Subtracted to
Nominal Production to Achieve Desired
Nominal Conductor Width.................................. 31
Table 3–9 Conductor Width Tolerances.............................. 32
Table 6–1 Packaging and Interconnecting Structure
Comparison........................................................ 51
Table 6–2
P & I Structure Selection Considerations .......... 52
Table 6–3
P & I Structure Material Properties.................... 52
IPC-SM-782A December 1999
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December 1999 IPC-SM-782A
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Surface Mount Design and Land Pattern Standard
1.0 SCOPE
This document provides information on land pattern geom-
etries used for the surface attachment of electronic compo-
nents. The intent of the information presented herein is to
provide the appropriate size, shape and tolerance of surface
mount land patterns to insure sufficient area for the appro-
priate solder fillet, and also to allow for inspection and
testing of those solder joints.
1.1 Purpose
Although, in many instances, the land pat-
tern geometries can be slightly different based on the type
of soldering used to attach the electronic part, wherever
possible, land patterns are defined in such a manner that
they are transparent to the attachment process being used.
Designers should be able to use the information contained
herein to establish standard configurations not only for
manual designs but also for computer aided design sys-
tems. Whether parts are mounted on one or both sides of
the board, subjected to wave, reflow, or other type of sol-
dering, the land pattern and part dimensions should be opti-
mized to insure proper solder joint and inspection criteria.
Although patterns are standardized, since they are a part of
the printed board circuitry geometry, they are subject to the
producibility levels and tolerances associated with plating,
etching, or other conditions. The producibility aspects also
pertain to the use of solder mask and the registration
required between the solder mask and the conductor pat-
terns. (See paragraph 1.2.2).
1.2 Performance Classification
Three general end-
product classes have been established in associated IPC
standards and specifications to reflect progressive increases
in sophistication, functional performance requirements and
testing/inspection frequency. It should be recognized that
there may be an overlap of equipment between classes.
Design requirements determine class. Class definitions are
useful for identifying degrees of precision needed to meet
design/performance requirements of packaging and inter-
connecting structures, and establish communication media
between design and manufacture and disciplines.
The printed board user has the responsibility to determine
the class to which his product belongs. The contract shall
specify the performance class required and indicate any
exceptions to specific parameters, where appropriate. In the
event of conflict between the design requirements and the
classes defined herein, the former shall take precedence
and be reflected in the master drawing.
These classes are:
CLASS 1 General Electronic Products
Includes consumer products, some computer and computer
peripherals, as well as general military hardware suitable
for applications where cosmetic imperfections are not
important and the major requirement is function of the
completed printed board or printed board assembly.
CLASS 2 Dedicated Service Electronic Products
Includes communications equipment, sophisticated busi-
ness machines, instruments and military equipment where
high performance and extended life is required, and for
which uninterrupted service is desired but is not critical.
Certain cosmetic imperfections are allowed.
CLASS 3 High Reliability Electronic Products
Includes the equipment for commercial and military prod-
ucts where continued performance or performance on
demand is critical. Equipment downtime cannot be toler-
ated, and functionality is required for such applications as
life support items, or missile systems. Printed boards and
printed board assemblies in this class are suitable for appli-
cations where high levels of assurance are required and
service is essential.
The land patterns in this standard have the capability of
accommodating all three performance classifications.
1.2.1 End-Use Applications
In addition to the three per-
formance classifications, the Surface Mount Council has
established end use applications for electronic products.
These are:
1. Consumer products including games, toys, audio and
video electronics. In general, convenient size and
maximum functionality are important but product cost
is extremely important.
2. General purpose computers, as used in businesses and
personal applications. Compared to consumer prod-
ucts, customers expect longer life and more consistent
service.
3. Telecom products including telephone, switching sys-
tems, PBXs, and exchanges. These products are used
in applications expecting long service life and endur-
ing relatively harsh environments.
4. Commercial aircraft requiring small size, light weight
and high reliability.
5. Industrial products and passenger compartment auto-
motive applications. Size and function is a byword of
these products. Cost is very important, provided that
reducing product cost doesn’t forfeit the highest
achievable product quality, performance, and function.
December 1999 IPC-SM-782A
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