IPC-CM-770D-1996.pdf - 第61页

IPC-CM-770

Januaty

1996

DIPS. This should extend the useful life of present day

technology for some high lead count applications.

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SOLID

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110

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II0

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PACKAQE

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Figure 13-2

110

Density Versus Lead Count (All

Dimensions in Inches)

13.1.2 Through-Hole Mounting

Through-hole mounting

is the dominant choice in pin grid array package applica-

tions.

Due to the high count of I/O pins the package can be

inserted in the present 100-mil grid through-hole process

and subjected to wave soldering.

Inspection of the solder connections under the package

body can be easily performed on the solder side of the

board and the device can be tested on existing "bed

of

nails" testers.

Inspecting the solder joints on the component side of the

board is extremely difficult without the aid of special tools

such as a fiber optic inspection system or a laser system

where joint temperature profile is indicative of the amount

of solder and integrity of the joint.

For this reason and because of the risks involved with

removal of these packages, sockets have been utilized (see

Figure

13-3).

Low profile grip sockets can also be used.

13.1.2.1 Component Preparation

Pin grid arrays con-

taining rigidized leads do not require lead forming prior to

assembly. They are through-hole mounted with straight

lead attach.

13.1.2.2 Land Patterns

When mounted directly to the

printed board, land patterns will be developed according to

the applicable class of the assembly. However, the lead

hole clearance should be

0.010-0.014

inch to allow for

placement variables and good capillary action of solder

flow.

Figure 13-3 Zero Insertion Force Socket

13.1.2.3 Lead Configuration After Assembly

Due to pin

density of pin grid array packages they can be mounted

with leads extending through the holes. Lead clinching is

not required.

13.1.3 Mixed Technology

The pin grid array being

through-hole mounted can be utilized along with other

through-hole components, DlPs, axial- leaded components,

etc. as part of a mixed assembly.

13.1.4 Manual Assembly

Manual assembly of the pin

grid array package to the printed board can be achieved by

using special tools designed for ease of alignment and

insertion. The operator can use a tweezer- type device to

place and hold a component, or a machine-positioned

vacuum pick-up under the operators control.

13.1.5 Automated Assembly

For high volume pin grid

array package assembly, high accuracy assembly robot

workcells represent a cost effective method of automating

semiautomatic and manual steps. The workcells can be

configured to perform a wide variety of insertion and

assembly tasks. Automated techniques for installing the

PGA to the board presently utilize robotic applications.

13.2 Surface Mount Area Arrays

This section provides

information on the design and assembly considerations for

the use of Surface Mount Grid Array packages. Generally,

they are known as Pad Grid Arrays or as Land Grid Arrays

(LGA). The terminations on the BGA packages are distrib-

uted over the bottom of the package and are solder

assembled to an area array of lands on a printed circuit

board. They are intended to provide high IO packaging of

integrated circuits in a small physical space with good reli-

ability, good assembly quality and low assembly cost.

Some have been registered under the JEDEC JC-11 proce-

dures of the EIA.

3

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Licensed by Information Handling Services

COPYRIGHT Association Connecting Electronics Industries

Licensed by Information Handling Services

January

1996

IPC-CM-770

The interconnections between the package and the sub-

strate (Printed Wiring Board structure) is typically made

with a solder pillar connecting the lands on the bottom of

the package and a set of matching lands on the substrate.

There are two common ways of forming the solder pillars.

In Ball Grid Arrays (BGA) an eutectic or near eutectic sol-

der ball is fused to the pads on the bottom of the package

during package manufacture. In assembly the solder balls

are reflow soldered to the substrate lands (with the assis-

tance of flux or solder paste). Since the solder ball is mol-

ten during assembly, the package has a tendency to self

center on the footprint producing a very robust assembly

process. The height of the solder pillar is determined by the

solder ball volume and the weight of the package. Ball

Grid Arrays are most common in plastic body packages.

In Column Grid Arrays (CGA) The solder pillars are cast

directly onto the package lands out of a high melting point

solder. They are soldered to the substrate footprint with

solder paste

so

that only the very bottom and the pillars

reflow. This provides a controlled height of the solder col-

umn (with an accompanying increase in fatigue lifetime) at

the cost of a less robust assembly procedure. CGAs are

most common in ceramic body packages.

The material in this section is specific to plastic packages

which have been registered under JEDEC. While ceramic

LGA packages are offered as custom devices by some sup-

pliers, they are not yet registered with the EIA and neither

design nor reliability information is available on them.

13.2.1 Ball Grid Arrays (BGA).

Surface Mount Plastic Ball Grid Array (PBGA or BGA)

packages are considered an alternative to finer pitch, higher

I/O packages. The packages is typically an overmolded, BT

resin glass/epoxy substrate. The BGA package distributes

the pin outs over the bottom of the package and are solder

assembled to a complimentary area array of lands on a

printed circuit board. The pin-outs are typically 30 mil

diameter solder spheres that are reflowed onto the pads of

the package. BGAs provide high I/O per unit area of pack-

age, are compatible with existing SMT assembly process,

reduce PWB and component requirements and improve

manufacturing yields. Because of these advantages over

peripheral leaded devices BGAs are receiving a lot of

attention.

Specific configuration details of Ball Grid Array packages

can differ due to package performance requirements. Over-

all, the package outline the assembly methods are common.

BGAs have been registered under the JEDEC JC-11 proce-

dures of the EIA.

13.2.1.1 Summary

of

BGA Requirement and Recom-

mendations

Solder joints shall not be touched up. Via-In-

Pad (VIP) technology shall not be used at present. PWB

footprint shall have circular lands matching each termina-

tion on the BGA package. The diameter of the PWB land

should be the same as the land on BGA.

13.2.1.2 Package Drawings

Figure 13-4 contains pack-

age outline drawings for plastic BGAs taken from the

JEDEC JC-11 registration documentation. The body sizes

are “Hard Metric” and are for square bodies with sym-

metrical array. The range of package sizes, pitches and the

maximum number of I/O allowed for that pitch are con-

tained in Table 13-1.

Table 13-1 Variations in BGA Package Sizes

Dimensions DIE in mm (See Figure

1)

Staggered matrices are allowed and are anticipated prima-

rily for higher lead count applications in the l.Omm and

1.27mm pitch families. Cavity-up package designs allow

for a full array of terminations on the bottom of the pack-

age and the number of available terminations can be equal

to the entries found in Table 13-1. Cavity-down designs,

for thermal dissipation, leave a region under the cavity that

is free of terminations. The size of the excluded region will

depend on the dimensions of the required cavity and is

specific to individual package designs.

Table 13-2 shows the acceptable BGA solder sphere

dimensions and package coplanarity as per the JEDEC

registration.

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COPYRIGHT Association Connecting Electronics Industries

Licensed by Information Handling Services

IPC-CM-770

Januaty

1996

Table 13-2 BGA Solder Sphere Dimensions and Package Coplanarity

All

Dimensions are in mm.

aaa =Coplanarity of solder spheres

bbb =Coplanarity of

BT

substrate

ccc =Coplanarity of overmolding

AI

=

Height of reflowed solder sphere on packaging

b

=

Solder sphere diameter

13.2.1.3 Assembly

BGA assembly has been proven to be consistent with the

best current practices (BCP) for surface mount (SM)

assembly. They can be assembled concurrently with periph-

eral leaded devices on a typical automated assembly line.

Paste is printed, packages are placed and then the boards

are reflowed. Reflow is typically done in an IRIConvection

oven with a nitrogen atmosphere with a profile similar to

those used for SM assembly. The assembly process of the

BGA is robust because the package tends to self center

during reflow and the molten ball can accommodate to

board or package planarity variations. Packages are avail-

able in trays or tape and reel and can be placed with stan-

dard placement machinery without special considerations.

They are currently a class

3

component and require special

handling. They must be used within 24 hours of their

removal from dry pack and must be stored in low humid-

ity once opened. The solder process is very robust for

BGAs.

Solder paste should be applied using a stencil having an

aperture of no greater than the pad diameter on all lands

with a stencil thickness no less than

6

mils. The assembly

process is relatively insensitive to solder paste thickness as

long as planarity is good enough for the solder paste to

make contact with both package and land.

Only the outer ring of solder terminations is accessible for

visual inspection. This along with measuring the collapse

of the package onto the board (approximately a 20 mil

standoff) is generally adequate for process control but does

not allow

100%

visual inspection of solder joints.

Repair can only be accomplished by total removal and

replacement of the BGA package. This can be done with

standard hot gas removal and replacement of the BGA

package. Solder joints shall NOT be touched up.

14.0 UNPACKAGED SEMICONDUCTOR COMPONENTS

There are several ways to package and assemble integrated

circuits (IC) on printed boards, see Figure 14-1.

The benefit of using Chip On Board (COB) technology all

stems from the absence of the IC package. The wire

bonded bare IC chip, COB, takes up about 114 of the area

of a Dual Inline Package (DIP) and is more space efficient

that Leadless Chip Carrier (LCC) packages. Lower profile

COB can be used in applications not possible with other

packaged chips, such as in “smart” credit cards. Trends in

low power CMOS type semi- conductor technology have

paved the way for the power limited COB technology.

14.1 Part Type Description

Semiconductor dice (chip)

types used in COB technology are comprised of back-

bonded chips and front bonded chips.

14.1.1 Back-Bonded Semiconductor Chips

Back-

bonded chips are components that install into discrete

packages. For example, in transistors the bottom of the

chip serves as the collector an metal lands serve as the base

and emitter. The chip’s collector is bonded directly to the

mounting substrate and discrete connections are made to

the base and emitter. For chip-on-board (COB) application,

chip-and-wire technology is ideally suited for use with the

back-bonded chips. The use of back-bonded chips has

advantages and disadvantages.

The advantages of using back-bonded chips are:

Availability: Most discrete IC come in chip form.

Small sizelhigh packaging densities.

Heat transfer: Intimate contact heat dissipation.

Cost: No additional processing by IC manufacturer.

The disadvantages of using back-bonded chips are:

Handling and testing is difficult due to small size.

Fragility: Susceptible to handling damage.

14.1.2 Face Bonded Semiconductor Chips

Face-

bonded chips have supplementary features that provide

access to its inputloutput lands. For COB applications,

common forms of these components include beam-tape,

TAB devices and flip chips. The use of face-bonded chips

has several advantages and disadvantages.

The advantages of using face-bonding chips are:

Mounting: Bonded circuit connections to metallization

accomplishes both mechanical mounting and electrical

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COPYRIGHT Association Connecting Electronics Industries

Licensed by Information Handling Services

COPYRIGHT Association Connecting Electronics Industries

Licensed by Information Handling Services