IPC-D-859.pdf - 第12页

Thick-ﬁlm circuit A microcircuit in which passive com- ponents of a ceramic-metal composition are formed on a suitable substrate by screening and ﬁring. Thick-ﬁlm hybrid circuit A hybrid microcircuit that has add-on comp…

card assemblies, and modules composed exclusively of dis-

crete electronic parts.)

Microcircuit module An assembly of microcircuits or an

assembly of microcircuits and discrete parts, designed to

perform one or more electronic circuit functions, and con-

structed such that for the purposes of speciﬁcation testing,

commerce, and maintenance, it is considered indivisible.

Micro-components Small discrete components such as

chip transistors and capacitors.

Microwave integrated circuit A miniature microwave

circuit usually using hybrid circuit technology to form the

conductors and attach the chip devices.

Monolithic ceramic capacitor A term sometimes used to

indicate a multilayer ceramic capacitor.

Monolithic integrated circuit An integrated circuit con-

sisting of elements formed in place on or within a semicon-

ductor substrate with at least one of the elements formed

within the substrate.

MOS device Abbreviation for a metal oxide semiconduc-

tor device.

Multichip integrated circuit An integrated circuit whose

elements are formed on or within two or more semiconduc-

tor chips which are separately attached to a substrate or

header.

Multichip microcircuit A microcircuit consisting solely

of active dice and passive chips which are separately

attached to the major substrate and interconnected to form

the circuit.

Nailhead bond See Ball bond.

Neck break A bond breaking immediately above gold

ball of a thermo-compression bond.

Off bond Bond that has some portion of the bond area

extending off the bonding land.

Overglaze A glass coating that is over another component

or element, normally for physical or electrical protection.

Package The container for an electronic component(s)

with terminals to provide electrical access to the inside of

the container. In addition, the container usually provides

hermetic and environmental protection for, and a particular

form factor to, the assembly of electronic components.

Package cap A cuplike cover that encloses the package

in the ﬁnal sealing operation.

Package lid A ﬂat cover plate that is used to seal a pack-

age cavity.

Packaging and Interconnecting (P/I) structure The gen-

eral term for a completely processed printed board, ceramic

substrate with interconnection wiring, or other combina-

tions of substrates and interconnection wiring, used for the

purpose of mounting components.

Purple plague One of several gold-aluminum compounds

formed when bonding gold to aluminum and activated by

re- exposure to moisture and high temperature. Purple

plague is purplish and very brittle, potentially leading to

time- based failure of the bonds. Its growth is highly

enhanced by silicon to form ternary compounds.

Push-off strength The amount of force required to dis-

lodge a chip device from its mounting land by application

of the force to one side of the device, parallel to the mount-

ing surface.

Resistor paste calibration The characterizing of a resistor

paste for Ω/square value, thermal coefficient of resistance,

and other speciﬁed parameters by screening and ﬁring a

test pattern using the paste and recording the results.

Sagging or wire sag The failure of bonding wire to form

the loop deﬁned by the path of the bonding tool between

bonds.

Search height The height of the bonding tool above the

bonding area at which ﬁnal adjustments in the location of

the bonding area under the tool are made prior to lowering

the tool for bonding.

Semiconductor carrier A permanent protective structure

which provides for mounting and for electrical continuity

in application of a semiconductor chip to a major substrate.

Semiconductors Solid materials such as silicon that have

a resistivity midway between that of a conductor and a

resistor. These materials are used as substrates for semicon-

ductor devices such as transistors, diodes, and integrated

circuits.

Serpentine cut A trim cut in a ﬁlm resistor that follows a

meandering repetitive pattern to effectively increase the

resistor length and increase resistance.

Smeared bond A bond impression that has been distorted

or enlarge by excess lateral movement of the bonding tool,

or by the movement of the device-holding ﬁxture.

Squash-out The deformed area of a lead which extends

beyond the dimensions of the lead prior to bonding.

Substrate (of a microcircuit or integrated circuit) The

supporting material upon which the elements of a hybrid

microcircuit are deposited or attached or within which the

elements of an integrated circuit are fabricated.

Tail (of the bond) The free end of wire extending beyond

the bond impression of a wire bond from the heel.

Tail pull The act of removing the excess wire left when a

wedge or ultrasonic bond is made.

Thick ﬁlm A ﬁlm deposited by screen printing processes

and ﬁred at high temperature to fuse into its ﬁnal form. The

basic processes of thick-ﬁlm technology are screen printing

and ﬁring.

December 1989 IPC-D-859

Thick-ﬁlm circuit A microcircuit in which passive com-

ponents of a ceramic-metal composition are formed on a

suitable substrate by screening and ﬁring.

Thick-ﬁlm hybrid circuit A hybrid microcircuit that has

add-on components, usually chip devices added to a thick-

ﬁlm network to perform an electronic function.

Thick-ﬁlm network A network of thick-ﬁlm resistors

and/or capacitors interconnected with thick-ﬁlm conductors

on a ceramic substrate, formed by screening and ﬁring.

Thick-ﬁlm technology The technology whereby electrical

networks or elements are formed by applying a liquid,

solid, or paste coating through a screen or mask in a selec-

tive pattern onto a supporting material (substrate) and fired.

Films so formed are usually 5 µm or greater in thickness.

Top hat resistors Film resistors having a projection out

one side allowing a notch to be cut into the center of the

projection to form a serpentine resistor and thereby

increase the resistivity.

Trim notch The notch made in a resistor by trimming to

obtain the design value.

Trimming Notching a resistor by abrasive or laser means

to raise the nominal resistance value.

Ultrasonic bonding A process involving the use of ultra-

sonic energy and pressure to join two materials.

Uncased device A chip device.

Via An opening in the dielectric layer through which a

conductive riser passes.

Wedge bond A bond made with a wedge tool. The term

is usually used to differentiate thermo-compression wedge

bonds from other thermo-compression bonds. (Almost all

ultrasonic bonds are wedge bonds.)

Wedge tool A bonding tool in the general form of a

wedge with or without a wire-guide hole to position the

wire under the bonding face of the tool, as opposed to a

capillary-type tool.

Wobble bond A thermo-compression, multi-contact bond

accomplished by rocking (or wobbling) a bonding tool on

the beams of a beam lead device.

3.2 Design Features The design features of the thick

ﬁlm multilayer hybrid circuits shall be in accordance with

this standard. Quality conformance test circuitry should be

included on each panel and shall be in accordance with

Section 6. Test circuitry shall be not more than 10 mm

[0.400 inch] and shall be not less than 5 mm [0.200 inch]

from the edge of the hybrid circuit, and shall reﬂect the

design of the circuit and all the manufacturing processes.

Quality conformance test circuitry shall also be included on

the master pattern, master drawing and artwork in accor-

dance with Section 6.

3.3 Documentation Package The designer shall estab-

lish the documentation package necessary to deﬁne, pro-

duce, and test a hybrid microcircuit which is adequate for

the customer’s end-use requirements. This section will

describe a typical documentation package that includes the

details required by the various disciplines involved with the

manufacturing processes.

3.3.1 Master Drawing Package The master drawing

package is composed of the various individual drawings, or

combinations necessary to speciﬁcally deﬁne the physical,

electrical, and environmental criteria applicable to the

hybrid microcircuit.

Master drawings shall be prepared in accordance with IPC-

D-325. Dimensioning and tolerancing practices used in

master drawings shall be in accordance with IPC-D-300.

3.3.1.1 Schematic The schematic is a diagram of a

functional electronic circuit consisting of symbols of all

active and passive elements and their interconnections that

form the circuit. The schematic should include the follow-

ing information:

1. Power supply voltages

2. Input signal requirements

3. Pin-out numbers and functions

4. Test points

5. Active and passive circuit element reference identiﬁca-

tion, part number, value, and tolerance.

3.3.1.2 Assembly Drawing The Assembly Drawing

shows package outlines with the components mounted in

their proper locations and denotes interconnection instruc-

tions. This drawing should contain:

1. Package outlines

2. List of material

3. Special handling (electrostatic discharge [ESD] cau-

tion, fragility, assembly environments, coatings, tailor-

ing, radiation- hardening, etc.)

4. Marking requirements (traceability, federal code, part

number, etc.)

5. Applicable procedures (Assembly Test Plan (ATP),

visual characteristics, customer speciﬁcations, etc.)

6. Component locations and provisions for use of alter-

nate components

7. Burn-in circuit and other conditions that may be a part

of other documentation, such as an ATP.

8. As-required material (e.g., wire, epoxy, etc.)

3.3.1.3 Artwork Artwork is required to produce:

1. Dielectric screens

2. Via screens

IPC-D-859 December 1989

3. Conductor screens

4. Overglaze screens

5. Solder screens

6. Thick ﬁlm masks

7. Marking artwork or stamps

3.3.1.4 Piece-Part and Material Procurement Specifica-

tions

Piece-part and material procurement speciﬁcations

deﬁne the physical, electrical, and environmental criteria

applicable to purchased items. Special requirements should

include shipping and packaging instructions, if required.

The conventional vehicle for these documents are Speciﬁ-

cation and Source Control drawings.

3.3.2 Viewing Unless otherwise speciﬁed, conductor lay-

ers shall be numbered consecutively, starting at the sub-

strate, as shown in Fig. 3–1.

3.3.3 Location Dimensioning All vias, test points, termi-

nal areas, and overall completed circuit dimensions shall be

dimensioned by use of a modular grid system, except

where necessary to mate parts not on grid. The choice of

the primary modular grid system used in the design of

hybrid circuits shall be metric (SI) and the basic modular

units of length shall be .5 mm and 0.05 mm; in that order

of preference, and shall be applied in the X and Y axis of

the Cartesian coordinates. The secondary modular grid sys-

tem is inch based, where the basic modular units of length

shall be 0.025 or other multiples of 0.005 inch; in that

order of preference, and shall be applied in the X and Y

axis of the Cartesian coordinates.

3.3.4 Hole Location Tolerance Unless otherwise speci-

ﬁed, the location of holes and/or vias shall be dimensioned

with respect to single or secondary grid systems.

3.3.5 Processing Allowances The processing allow-

ances which were considered in the design and artwork

preparation for the hybrid circuit shall be documented and

deﬁned on the master drawing in accordance with IPC-D-

325, in either note form, or by reference to another draw-

ing which contains artwork speciﬁcations (see Section 5).

3.3.6 Datums There shall be a minimum of two datum

features to establish the mutually perpendicular datum ref-

erence frame for each circuit. Each datum shall be estab-

lished by at least two holes, points, symbols, or other

datum features, but not edges, and be included on all con-

ductive layers. Critical design features may require the use

of more than one set of datum references. The master

drawing shall establish the relationship and acceptable tol-

erance between all datum features. All datum features shall

be located on grid, or establish grid criteria, as deﬁned on

the master drawing, and should be within an outline of the

hybrid circuit.

3.4 Electrical Requirement Considerations

3.4.1 Conductor Thickness and Width

The minimum

width and thickness of conductors on the ﬁnished circuit

should be determined on the basis of the current-carrying

capacity required, and the maximum permissible conductor

temperature rise; processing allowances (see 3.3.5) shall be

considered in the evaluation. Conductor width and thick-

ness values shall be not less than the dimensions estab-

lished in Table 3–1. In general, the designer should base

dimensions on supplier data for the speciﬁc conductor

material used. For impedance/capacitance control consider-

ations see paragraph 3.4.3. For ease of manufacture and

durability in usage, these parameters should be maximized

while maintaining the minimum recommended spacing

requirements deﬁned herein (see Table 3–1).

3.4.2 Electrical clearance Spacing between conductors

on individual layers (same plane) in multilayer hybrid cir-

cuits shall be in accordance with the requirements of Table

3–1.

3.4.3 Impedance/Capacitance Control Considerations

Multilayer hybrid circuits are ideally suited for providing

interconnection wiring that is speciﬁcally designed to pro-

vide desired levels of impedance and capacitance control.

Techniques commonly referred to as ‘‘strip-line,’’ or

‘‘embedded microstrip,’’ (see Figure 3–5) are particularly

suited for impedance and capacitance requirements.

As shown in Figure 3–5, there are four basic types of

transmission line constructions. These are:

1. Microstrip or ‘‘open-line,’’ where the external center

conductor is separated from the reference plane

(shield) by a single thickness of dielectric material.

2. Embedded microstrip, where the center conductor is

bounded on all sides by dielectric material that sepa-

rates it from a single reference plane (shield).

3. Balanced stripline, where the center conductor is

bounded on all sides by dielectric material that sepa-

rates it equally from two reference planes.

4. Unbalanced stripline, where two or more layers of con-

ductors are separated from a combination of reference

planes in an unbalanced conﬁguration.

The characteristic impedance of a microstrip can be calcu-

lated using the formula:

√

+ 1.41

(5.98h)

(0.8W + t)

where e

= relative dielectric constant of substrate material

(see Table 3–5)

w,h,t are dimensions indicated in Figure 3–7.

The most commonly used microwave circuit technique is

microwave stripline (Figure 3–6A). Stripline energy is

December 1989 IPC-D-859