IPC-D-859.pdf - 第48页

the IPC-D-350 series, to facilitate the interchange of infor- mation between automated systems. Archiving of data shall be in accordance with IPC-D-350, IPC- D-351, IPC-D-352, IPC-D-353 and IPC-D-354. W ith automated tec…

to structure this information so that there can be no misun-

derstanding for anyone viewing the layout. Notes are espe-

cially important for the engineering review cycle, the digi-

tizing effort, and when the document is used by someone

other than the originator.

5.1.5.6 Automated Layout Techniques All of the infor-

mation contained in 5.1.5 through 5.1.5.6 is applicable to

both manual and automated layout generation. However,

when automated layout techniques are used, it is also nec-

essary that they match the design system being employed.

This may include the use of computer-aided-drafting assis-

tance that primarily helps in the deﬁning of components

and conductors, or may be as sophisticated as to add the

placement of gates, the placement of components, and/or

the routing of conductors.

When automated systems must communicate with each

other, it is recommended that standard ﬁles be used for this

technique. A standard format has been developed, such as

IPC-859-5-1

Figure 5–1 Simpliﬁed ﬂow chart of hybrid circuit design/fabrication sequence

▼

▼▼ ▼

▼

▼▼

▼▼▼

▼▼

▼

▼▼

▼

▼▼▼▼▼

Assembly

Test

Hole &

Process

Data

Panel or 

Printed Board 

(Rigid or Flexible)

Assembly

Sequence/

Process Data

Printed

Board

Assembly

Parts

List

Schematic/Logic

Diagram

End Product

Specification

CAD

Library

Test

Coupon

Manual

Layout

Tape 

Masters

Digitize for

N/C as Required

Other

Documentation

Manual

Layout, Digitize

Manual

Layout, Digitize

Input Data and

Circuit Analysis

Input Data and

Circuit Analysis

Photoplot

Masters

N/C Tape

Output

Other

Documentation

Other

Documentation

Other

Documentation

Other

Documentation

N/C Tape

Output

N/C Tape

Output

N/C Tape

Output

Interactive Edit.

and Rules Check

Batch D/A Place

and Route

Interactive Place

and Route

Photoplot

Masters

Photoplot

Masters

Photoplot

Masters

On Line or Follow

on Rules Check

Interactive Completion

In Real Time

Manual Complete

if Required

SINGLE OR MULTIPLE IMAGE PRODUCTION MASTER ORIGINALS

1-Manual 2-Manual/Digitize

3-Computer 

Aided Drafting

4-Design Automation

(DA) (Batch)

5-Computer Aided Design

(CAD)--Interactive

▼

December 1989 IPC-D-859

the IPC-D-350 series, to facilitate the interchange of infor-

mation between automated systems.

Archiving of data shall be in accordance with IPC-D-350,

IPC- D-351, IPC-D-352, IPC-D-353 and IPC-D-354.

With automated techniques, the data base should include

the completeness of all information that will produce the

hybrid circuit. As required, this will include all notes, plat-

ing requirements, substrate thickness, etc. The use of a

check plot is important tohelp verify that the data base

matches the requirements, as necessary.

5.2 Substrate Geometries

5.2.1 Size and Shape

The size and shape of a hybrid

substrate can be of critical importance. Because of the

brittle nature of typical hybrid substrates (ceramics), care

must be exercised in both the design outline layout and

material selection.

• Route test/control points to the edge connector to enable

monitoring and driving of internal circuit functions and to

assist in fault diagnosis.

• Divide complex logic functions into smaller, combina-

tional logic sections.

• Avoid one-shots; if used, route their signals to the edge

connector.

• Avoid potentiometers and ‘‘select-on-test’’ components.

• Use a single, large-edge connector to provide I/O pins and

test/control points.

• Make PC-board I/O signals TTL-compatible to keep ATE

interface costs low and give ﬂexibility.

• Provide adequate decoupling at the board edge and locally

at each IC.

• Provide signals leaving the hybrid with maximum fan-out

drive, or buffer them

• Buffer edge-sensitive components from the edge

connector—such as clock lines and ﬂip-ﬂop outputs.

• Never exceed the logic rated in-out; in fact, keep it to a

minimum.

• Avoid devices that require high-fan-outs.

• Keep logic depth on any hybrid to a low level by using

edge-terminated test/control points.

• Single-load each signal entering the hybrid whenever pos-

sible.

• Terminate unused logic pins appropriately to minimize

noise pick-up.

• Do not terminate logic outputs directly into transistor

bases. Do use a series current-limiting resistor.

• Buffer ﬂip-ﬂop output signals before they leave the

hybrid.

• Use open-collector devices with pull-up resistors to

enable external override control.

• Avoid using redundant logic to minimize undetectable

faults.

• Bring outputs of cascaded counters to higher-order

counters so that they can be tested without large counts.

• Construct trees to check the parity of selected groups of

eight bits or fewer.

• Avoid wire-OR and wire-AND connections. If you can’t,

use gates from the same IC package.

• Provide some way to bypass level-changing diodes in

series with logic outputs.

• Break paths when a logic element fans out to se veral

places that converge later.

• Use elements in the same IC package when designing a

series of inverters or inverters following a gate function.

• Standardize power-on and ground pins to avoid test-

harness multiplicity.

• Bring out test points as near to d/a conversions as pos-

sible.

• Provide a means of disabling on-board clocks so that the

tester clock may be substituted.

• Provide mounted switches and RC networks with over-

ride lines to the edge connector.

• Route logic drives of lamps and displays to the edge con-

nector so that the tester can check for correct operation.

• Separate analog circuits from digital logic, except for tim-

ing circuits.

• Uniformly mount ICs and clearly identify them to make it

easier to locate them.

• Provide sufficient clearance around IC sockets and direct-

soldered ICs so that IC clips can be attached whenever

necessary.

• Add top-hat connector pins or mount extra IC sockets

when there aren’t enough edge-connector pins for test/

control points.

• Use sockets with complex ICs—CPUs, UARTs, and long,

dynamic shift registers.

• Wire feedback lines and other complex circuit lines to an

IC socket with a jumper plug so that they can be inter-

rupted at test.

• Use jumpers that can be cut during debugging. The jump-

ers can be located near the connector.

• Fix locations of power and ground lines for uniformity

among several hybrid types.

• Make the ground trace large enough to avoid noise prob-

lems.

• Group together signal lines of particular families.

• Clearly label all parts, pins, and connectors

Figure 5-2 Testability design checklist

IPC-D-859 December 1989

Generally, the hybrid designer should make certain that his

selection of materials is:

• physically capable of supporting the components and,

• sufficiently thick to withstand shock and vibration

requirements (varies with size).

Finally, design outlines should be of simple geometries

such as orthogonal quadrilaterals or circles. Designs which

employ sharp internal corners should be avoided because

of the stress risers they present and the greater potential for

breakage.

5.2.1.1 Material Size Considerations While multilayer

hybrid substrates of up to 19,350 sq. mm [30 sq. in.] have

been successfully fabricated, the designer must keep in

mind the normal limitations of equipment use in both the

fabrication and assembly of multilayer hybrid circuits. It is

recommended that the designer check with his fabricators

and assemblers before embarking on a design of unusual

dimensions.

The lidding of packages is also a concern. Lids on metal

cans not only hermetically seal the hybrid but can act as a

mechanical reinforcement. However, if the hybrid is exces-

sively large or of a poorly chosen material, the heat of sol-

dering on the lid can result in a latent mismatch in CTE

stressing the device and making it subject to failure by

either cracking of the substrate or popping off of the lid.

5.2.1.2 Quality Conformance Test Coupons Test cou-

pons, when required for process/quality control, are situ-

ated in such a manner that they are representative of the

board processing; are characteristic of the product, and

meet the requirements of IPC-HM-860.

5.2.2 Dimensions and Tolerances Where appropriate,

dimensions and tolerances shall be in accordance with

IPC-D- 300.

5.2.3 Datums Datums shall meet the requirements of

paragraph 3.3.6 (See Figure 5–3 for the establishment of

datum references.)

5.2.4 Thickness Considerations Symmetrical construc-

tions play a major role in allowing a hybrid manufacturer

the ability to minimize bow. Constructions which are

asymmetric induce greater warpage. Finished circuits

should have a minimum of 0.035 mm [0.0014 inch] of

dielectric material between conductive layers.

Overall thickness shall include metallic deposition and

shall be speciﬁed on the master drawing. In critical areas,

such as connector contact areas, the thickness tolerances

may be more stringent and shall be detailed on the master

drawing, and should, wherever possible be limited only to

those areas where needed.

In order to allow the manufacturer to use the most

dimensionally-stable and cost-effective materials for their

process, the designer minimizes the number of tolerances

invoked on the lay-up. In general, the following toleranc-

ing is appropriate:

Class A—A tolerance should only be placed on the overall

thickness.

Class B—A tolerance should only be placed on the overall

thickness and on the dimensions between a few selected

layers.

Class C—Tolerances can be placed on all of the spaces

between layers. A tolerance can also be placed on the over-

all thickness if the tolerance is sufficiently large to accom-

modate the accumulation of the tolerances between layers.

If the overall thickness tolerance is not sufficiently large,

the manufacturer might not be able to fabricate the circuit

or he may be required to selectively choose the materials

for the lay-up, which is very expensive.

5.2.5 Substrate Edges One substrate edge should be

located from a datum and, where applicable, other edges

should be dimensioned from that same datum.

5.3 Circuit Features

5.3.1 Conductors

Conductors on the hybrid circuit may

take a variety of shapes, they may be in the form of single

conductor traces, or conductor planes.

Due to screen printing variables and conductor ﬂow-out

after printing, processing allowances should be built into

the design, to allow the manufacturer to produce a part that

will meet the end-product requirements detailed on the

master drawing. For a typical high resolution conductor,

the width of the screen pattern will be 0 to 25 µm smaller

than the corresponding width speciﬁed for the ﬁred ﬁlm.

Conductors without high resolution properties may require

the allowance to be as great as 50 µm.

5.3.1.1 Conductor Width and Thickness The width and

thickness of conductors on the ﬁnished circuit shall be

determined on the basis of the current-carrying capacity

required, and the allowable temperature rise.

For ease of manufacturing and durability in usage, conduc-

tor width and spacing requirements should be maximized

while maintaining the minimum spacing requirements of

Table 3–1.

5.3.1.2 Conductor Routing The length of a conductor

between any two terminal areas should be held to a mini-

mum.

Conductor and resistor patterns should be oriented in the

‘‘X’’ and ‘‘Y’’ axes as shown in Figure 5–4.

December 1989 IPC-D-859