IPC-D-859.pdf - 第32页

thermal contact with the substrate along their entire length, shall be determined as follows: Where: d = S l K D 2 / 3 d = Minimum diameter of wire (see T able 3–14) I = Maximum continuous current (amp) K = Constant fact…

Q. Reliability—Assembled hybrid microcircuits should be

able to withstand the temperature-cycling, thermal-

shock and constant-acceleration tests deﬁned in MIL-

STD-883.

A list of some of the better know general types of attach-

ment materials, and their associated advantages and limita-

tions, is given in Table 3–12.

3.8.9 Chip to Substrate Interconnect Gold or alumi-

num wire bonds are used to interconnect the semiconduc-

tors and IC’s to the hybrid network and to the I/O pins. The

wires are bonded from the chip to a metallized bonding

land that is connected to the circuitry or the I/O pins.

The gold wires are typically alloyed with small amounts of

beryllium or copper to control grain growth during bond-

ing. The aluminum wires are typically alloyed with

approximately 1% silicon.

The following factors will inﬂuence the choice of wire

bonding materials and equipment:

A. Maximum processing temperature, including rework

(see Table 3–13)

B. Size of the bond sites on the semiconductor or IC 0.025

mm [0.001 inch) diameter wire thermo-sonic ball bond-

ing requires land sizes greater than 0.06 mm [0.0025

inch] square

C. Hybrid substrate conductor materials

D. Final operating and non-operating environment

E. The geometry of the hybrid package which may restrict

bonding tool access.

3.8.9.1 Bonding Process The choice of wire type and

speciﬁc properties, such as hardness, tensile strength and

percent elongation, are a function of the bonding process

used as well as speciﬁc bonding parameters. The standard

wire bonding process used for hybrids is thermosonic gold

ball-bonding. The principal advantages of this process are

the low substrate temperatures (<150°C) required and the

ability to bond in any direction.

Wedge bonders, used most frequently with aluminum wire,

require that the second bond be positioned directly behind

the ﬁrst. This is time consuming because the entire hybrid

package must be rotated to position each bond.

3.8.9.2 Gold and Aluminum Wire Selection The fusing

current of wire is dependent on the material, its diameter,

its length and application of the wire. The application is

important because it determines the operating temperature

and the degree of heat sinking required to the I/O leads or

substrates.

Table 3–14 lists sizes and typical current rating for alumi-

num and gold wires. Note: Most hybrid package leads are

made of Kovar [Fe, Co. Ni alloy] and are subject to I

heating effects.) Most leads should be limited to less than

0.5 amps.

Wire leads used to interconnect semiconductors to the

hybrid network, and/or package I/O pins that are not in

Table 3–12 The Advantages and Limitations of Various Adhesive Types

Type Advantages Limitations

Phenolics Very high bond strength Used mostly for structural applications, possibly corro-

sive, difficult to process at low temperatures

Polyurethanes Easy to rework Not suitable for temperatures above 120°C, relatively

high outgassing, some decomposition

Polyamides Easy to rework High moisture absorption, high outgassing, variations

in electrical insulation properties, especially when

exposed to high humidity

Polyimides Very-high temperature stability High cure temperatures, require solvents as vehicles

Silicones High’temperature stability, easy to rework, high purity,

low outgassing

Moderate-to-poor bond strength, high coefficient of

thermal expansion

Epoxies Some are easy to rework by thermomechanical

means, some are low outgassers, easy to process,

can be ﬁlled to 6-–70 percent with a variety of conduc-

tive or nonconductive ﬁllers

Depending on the type of curing agent used and

degrees of cure: outgassing, catalyst leaching, corro-

sivity

Cyanoacrylates Very rapid setting (10 sec), give very high initial bond

strengths

Bond strengths often degrade under moist or elevated

temperature (≤150°C) conditions

Glass–Silver Die

Attach Materials

High bond strength, with bond stable at high tempera-

tures. Non-corrosive with low moisture absorption and

little, if any outgassing.

Requires high cure temperature and is not easily

reworkable. Contaminant level fair to good.

Eutectic Alloy No outgassing. Good electrical and thermal properties.

Rapid setting.

Restricted in die size. Not repairable.

Solder No outgassing. Good electrical properties. Rapid set-

ting. Repairable.

Temperature sensitive for subsequent assembly pro-

cesses. High CTE.

December 1989 IPC-D-859

thermal contact with the substrate along their entire length,

shall be determined as follows:

Where: d =

2/3

d = Minimum diameter of wire (see Table 3–14)

I = Maximum continuous current (amp)

K = Constant factor based on length of metal wire (see

Table 3–15)

Both gold and aluminum ﬁne wire, in sizes from 0.0125

mm [0.0005 inch] 0.05 mm [0.002 inch] and may be pur-

chased in increments of 0.0025 mm [0.0001 inch]. The

procurement of both gold and aluminum wire is made

much easier by referring to the ASTM F-72 and ASTM

F-487, respectively. Fine aluminum wire with 1 percent

magnesium is speciﬁed in ASTM F-638. Larger sizes of

wire are available in diameters of 0.08, 0.13, 0.20, 0.25 and

0.38 mm [0.003, 0.005, 0.008, 0.010 and 0.015 inch].

3.8.10 Tape Automated Bonding (TAB) The TAB tape

patterns consist of gold or tin plated copper typically on a

polyimide carrier ﬁlm. Copper thicknesses from 0.018 to

0.071 mm [0.0007 to 0.0028 inch] and polyimide thick-

nesses from 0.013 to 0.13 mm [0.005 to 0.005 mm] are

readily available. Typically gold plating ranges from

0.0005 to 0.0013 mm [20 to 50 microinches] and a nickel

barrier can be provided between the gold and the copper if

high temperature service is required.

The TAB process involves additional wafer level process-

ing to provide a raised bump over the bond land to which

the TAB tape is attached. Bumps are either plated or evapo-

rated onto the wafer, and are usually gold or solder (Pb/

Sn). The following is a typical process ﬂow for the plating

of gold bumps onto a wafer.

– Wafer metallization (ex. TiW/Au, Ti/Pt/Au)

– Photoresist (application, exposure, develop, and bake)

– Bump plating (25 microns)

– Photoresist strip

– Thin ﬁlm metallization strip

– Wafer saw

3.8.10.1 Bonding Processes There are two types of

Table 3-13 Summary of Chip Interconnection Techniques

Wire Diameter

mm [inch] Attachment Method

Substrate

Temperature

(°C) Comments

(Gold) 0.018–0.025

[0.0007–0.001]

Thermocompression (hot substrate) >300 Limited repair ability

(Gold) 0.018–0.051

[0.0007–0.002]

Thermosonic ball or wedge 25 Quality of bonds improved if the substrate

is raised to 125°C. Can bond chips with-

out raising substrate temperature.

(Aluminum)

0.018–0.25

[0.0007–0.010]

Ultrasonic wedge 25 Low-temperature process, restricted due

to tool size

Table 3–14 Aluminum and Gold Wire Sizes and Current Rating

Wire Minimum

Diameter mm

[inch]

Standard Wires Resistance Ω/mm [Ω/ft.]

Aluminum Gold

Aluminum

1% Si

(Hard)

Aluminum

1% Si

(Annealed) Gold

0.018 [0.0007] X 1.1–1.2

[36.06–39.86]

1.06–1.26

[34.62–38.273]

0.91–0.96

[27.71–29.43]

0.025 [0.001] X X 0.58–0.64

[17.67–19.53]

0.52–0.62

[16.0–18.75]

0.44–0.47

[13.58–14.42]

0.051 [0.002] X 0.14–0.16

[4.41–4.88]

0.14–0.15

[4.23–4.68]

0.11–0.12

[3.40–3.61]

1. ASTM F487

2. ASTM F72

Table 3–15 Constant ‘‘K’’ Factor for Aluminum and Gold Wire

Length mm [inch] Aluminum (K) Gold (K)

≤1.02 [0.040] 171.8 [22,000] 234 [30,000]

>1.02 [0.040] 119 [15,200] 160 [20,500]

1. ASTM F72

IPC-D-859 December 1989

bonds which need to be made when using TAB: innerlead

and outerlead. The innerlead bond is made between the die

and the TAB tape, and the outerlead bond occurs from the

tape to the thick-ﬁlm substrate or circuit board.

Innerlead bonding is typically a gang thermocompression

process. The die is placed on a heated stage, the TAB tape

is optically aligned to the die, a heated bonding tool applies

pressure to the bond lands, and all of the bonds are made

simultaneously. The bonding temperatures, pressures and

dwell times are dependent on: bond land size, number of

bond lands, and bump/tape metallurgies.

Innerlead bonding can also be accomplished using a single

point ultrasonic process. This process is very similar to the

wire bonding process and usually with simple conversions

the same machine can accommodate both processes. Single

point bonding is most applicable with very large or high

I/O (200+) die when the leveling of a gang bonding tool

could become cumbersome.

After innerlead bonding has occurred the die is attached to

a TAB tape carrier and can be fully electrically tested over

both temperature and speed. The die can also be burned in

at this time to insure that only electrically perfect dice are

committed to the hybrid or multichip module.

The next step is outerlead bonding and is a reﬂow, thermo-

compression, or thermosonic process. These can be either

gang or single point as well. The type is dependent on the

TAB tape plating type, the substrate or circuit board, the

operating environment of the system, and the level of

repairability required. Typically a gang reﬂow process

would be used on an epoxy glass board and a single point

thermosonic process would be utilized for a ceramic thick-

ﬁlm hybrid substrate.

3.8.11 Components The selection of component parts,

in accordance with reliability goals and contract require-

ments, inﬂuences the design of devices that will be both

reliable and qualiﬁed for production. The parts selection

process for hybrid use requires additional considerations

beyond that for conventional printed wiring components.

Every circuit conﬁguration and applied environment will

have internally and externally produced capacitive and

inductive components that could affect circuit performance.

As a rule, increasing the frequency of operation will

require closer attention to devices that must be attached

directly to the thick- or thin-ﬁlm substrate. These elements

are generally divided into two types, i.e. active and passive.

The active components are virtually always pre-selected by

the circuit-design engineer and appear on the hybrid sub-

strate as an add-on chip, while the passive components can

be an integral part of the thick- and/or thin-ﬁlm deposition

or add-on chips.

Active devices are semiconductor chips such as diodes,

transistors, and monolithic integrated circuits. The die is

the most common conﬁguration for the active device

assembly, and, in the unleaded, unbumped, chip form,

requires wire bonding from the chip to the substrate.

Beam-lead devices have preprocessed leads protruding past

the die edges to facilitate component attachment to the

substrate in a face-down condition.

Flip-chip devices have been processed to provide a solder

bump to enable the device to be mounted face down on a

mounting land pattern on the substrate.

Packaged devices have been employed to provide a sealed

device in a small package for attachment to the substrate.

Examples of these are chip carriers and epoxy-encapsulated

packages.

The use of packaged devices is inexpensive, fast, and

allows for pretesting and burn-in, but they require a signiﬁ-

cantly larger amount of substrate area than do unpackaged

devices. Packaged devices are typically mounted using sol-

der reﬂow techniques. However, conductive epoxy may be

used if the solder reﬂow temperatures are too high.

3.8.11.1 Integrated Circuits (Active Devices) Each

manufacturer’s die and topography is different from that of

any other manufacturer. Therefore, die bonding patterns

and chip sizesfrom different manufacturers should be

examined to optimize part selection. (Caution: It is easy to

design with the smallest possible component but, if the

source becomes nonexistent or delivery is not within limits

of the program, hybrid layout may be in jeopardy.)

3.8.11.1.1 Substrate Potential Many integrated circuit

substrates perform an integral role toward providing proper

performance of the device. Depending upon the type of

device, the substrate may be required to ﬂoat or to be tied

to the most negative potential.

3.8.11.1.2 Electrical Limitations Unlike packaged

devices, extensive testing cannot be performed on compo-

nents that are in the die form. Thus, circuit designs that

require low current/voltage offsets, AC responses, or tem-

perature responses, might not function because of the

inability to select (test) the die with probe testing. The test-

ing of die components is generally limited to DC param-

eters at 25°C or, in some instances, at elevated tempera-

tures.

3.8.11.1.3 Visual Inspection Although only limited test-

ing can be accomplished in the unpackaged state, 100%

visual inspection to MIL-STD-883 can and should be per-

formed.

3.8.11.1.4 Confidence Testing A sample quantity of

selected devices may be packaged and evaluated through

test and burn-in. While this will not indicate exactly how

December 1989 IPC-D-859