IPC-D-859.pdf - 第8页

IPC-HM-860 Speciﬁcation for Multilayer Hybrid Circuits 2.2 Government Documents 2.2.1 Military MIL-C-14450 Copper Plating (Electro-deposited) MIL-M-38510 General Speciﬁcation for Microelectronics MIL-G-45204 Gold Plating…

Design Standard for Thick Film

Multilayer Hybrid Circuits

1.0 SCOPE

This standard covers the requirements and considerations

for the design of multilayer hybrid circuits based on indus-

try manufacturing capabilities.

1.1 Purpose The purpose of this standard is to establish

rules, principles, and other considerations for mechanical,

electrical, and producible properties which the designer can

use to select design features, and properties that will result

in a multilayer hybrid circuit that will meet performance

and cost requirements.

1.2 Classification When appropriate, this standard will

provide three design complexity classes of features, toler-

ances, or measurements which reﬂect progressive increases

in sophistication of tooling, materials, or processing and,

therefore, progressive increases in cost. These classes are:

A) Simple, B) Moderate, and C) Complex. The use of one

class for a speciﬁc feature does not mean that other fea-

tures must be of the same class. Selection should be based

on the minimum need. In the event of conﬂict between the

design requirements and the classes deﬁned herein, the

former shall take precedence and be reﬂected on the mas-

ter drawing.

Design requirements such as precision, performance, and

conductive pattern density determine class. Class deﬁni-

tions identify the precision needed to meet design/

performance requirements of the hybrid circuit.

Classiﬁcation of design complexity requirements should

not be confused with the performance classiﬁcation of end-

item use, as referenced in other IPC documentation, such

as IPC-HM-860, which refers to Class 1—consumer prod-

ucts; Class 2—general industrial; and Class 3—high reli-

ability equipment types. The need to apply certain design

concepts should depend on the complexity and precision

required to produce a particular hybrid circuit. Any design

class for any circuit characteristic may be applied to any of

the end-product equipment categories and the classes

described from each, as required. Therefore, a consumer

product designated as Class 1 could require Class A, B or

C design complexity for different attributes of the circuit.

1.2.1 Circuit Type The multilayer hybrid circuit types

deﬁned in the IPC-HM-860 include both refractory and

nonrefractory metal co-ﬁred types (Type I) and thick ﬁlm

and thin ﬁlm inorganic types (Type II).

This standard will address only Type II(a), thick ﬁlm inor-

ganic multilayer hybrid circuits.

1.3 Presentation All dimensions and tolerances are

expressed in metric [and inches, shown in brackets], and

are not direct conversions. Users should employ a single

system, and not intermix millimeters and inches. Reference

information is shown in parentheses ( ).

2.0 APPLICABLE DOCUMENTS

The following documents, of the issue currently in effect,

form a part of this document to the extent speciﬁed herein.

2.1 IPC

IPC-T-50

Terms and Deﬁnitions

IPC-D-300 Dimensions and Tolerance for Printed Wiring

Applications

IPC-D-310 Guidelines for Artwork Generation and Mea-

surement Techniques

IPC-D-325 End-Product Documentation for Printed Wiring

Boards

IPC-D-350 End Product Description in Numeric Form

IPC-D-351 Printed Wiring Board Documentation in Digi-

tal Form

IPC-D-352 Electronic Design Data Base Description for

Printed Boards

IPC-D-353 Automatic Test Information Description in

Digital Form

IPC-D-354 Library Format Description for Printed Board

Digital Data Bases

IPC-TM-650 Test Methods Manual

IPC-SM-780 Guidelines for Component Packaging and

Interconnection with Emphasis on Surface Mounting

IPC-SM-782 Surface Mount Land Patterns (Configurations

and Design Rules)

IPC-CC-830 Qualiﬁcation and Performance of Electrical

Insulating Compounds for Printed Board Assemblies

IPC-SM-840 Permanent Polymer Coating (Solder Mask)

for Printed Wiring Boards

IPC-HM-855 Microelectronics Design Guide

December 1989 IPC-D-859

IPC-HM-860 Speciﬁcation for Multilayer Hybrid Circuits

2.2 Government Documents

2.2.1 Military

MIL-C-14450

Copper Plating (Electro-deposited)

MIL-M-38510 General Speciﬁcation for Microelectronics

MIL-G-45204 Gold Plating (Electro-deposited)

MIL-P-81728 Plating, Tin-Lead (Electro-deposited)

MIL-STD-883 Test Methods and Procedures for Microelec-

tronics

2.2.2 Federal

QQ-N-290

Nickel Plating (Electro-deposited)

QQ-S-571 Solder; Tin Alloy; Lead-Tin Alloy; and Lead

Alloy

2.3 Other Publications

2.3.1 ASTM

F72

Gold Wire for Semiconductor Lead Bonding

F 487 Fine Aluminum—1% Silicon Wire for Semicon-

ductor Lead Bonding

F 638 Fine Aluminum—1% Magnesium Wire for Semi-

conductor Lead Bonding

2.3.2 EIA

JEDEC Publication 95

Registered and Standard Outlines

for Solid State Products

3.0 DESIGN CONSIDERATIONS

The information contained in this document describes gen-

eral and speciﬁc requirements for the design of thick ﬁlm

multilayer hybrid circuits intended to meet the performance

and end product requirements of IPC- HM-860.

The success or failure of a hybrid design depends on many

interrelated considerations. The effect of the following

parameters on the design should be considered:

1. Equipment environmental conditions, such as ambient

temperature, heat generated by the components, and

ventilation.

2. Maintenance philosophy during the service life of the

equipment, especially with respect to component

placement that affects component accessibility.

3. Spacing between circuits particularly ‘‘mother board/

daughter board’’ designs that might affect placement on

interconnecting lead frames.

4. Testing/fault location requirements that might affect

component placement, conductor routing, connector

contract allocations, etc.

5. If an assembly is to be repairable, consideration must

be given to component/circuit density and the selection

of board/conformal coating materials. In general,

design should promote ease of package repair which

must be initiated by delidding.

3.1 Terms and Definitions Deﬁnitions of all terms used

herein shall be as speciﬁed in IPC-T-50 and as follows.

Abrasive trimming Trimming a ﬁlm resistor to its nomi-

nal value by notching resistor with a ﬁnely adjusted stream

of an abrasive material, such as aluminum oxide, directly

against the resistor surface.

Active trim Trimming of a circuit element (usually a

resistor) in a circuit that is electrically activated and oper-

ating to obtain a speciﬁed functional output for the circuit

(see Functional trimming).

Add-on component Discrete or integrated prepackaged or

chip components that are attached to a ﬁlm circuit to com-

plete the circuit functions.

Analog circuits Circuits that provide a continuous (vs.

discontinuous) relationship between the input and output.

Aspect ratio The ratio between the length of a ﬁlm resis-

tor and its width; equal to the number of squares of the

resistor.

Back bonding Bonding active chips to the substrate

using the back of the chip, leaving the face, with its cir-

cuitry face up. The opposite of back bonding is face down

bonding.

Back mounting See Back bonding.

Ball bond A bond formed when a ball shaped end inter-

connecting wire is deformed by thermo-compression

against a metallized land; also called ‘‘a nail head bond’’

from the appearance of the ﬂattened ball.

Beam lead A long structural member not supported

everywhere along its length and subject to the forces of

ﬂexure, one end of which is permanently attached to a chip

device and the other end intended to be bonded to another

material, providing an electrical interconnection or

mechanical support or both.

Beam lead device An active or passive chip component

possessing beam leads as its primary interconnection and

mechanical attachment means to a substrate.

Bond An interconnection which performs a permanent

electrical and/or mechanical function.

Bond deformation The change in the form of the lead

produced by the bonding tool, causing plastic ﬂow, in mak-

ing the bond.

IPC-D-859 December 1989

Bond envelope The range of bonding parameters over

which acceptable bonds may be formed.

Bond interface The interface between the lead and the

material to which it was bonded on the substrate.

Bond lift-off The failure mode whereby the bonded lead

separates from the surface to which it was bonded.

Bond off See Bond lift-off.

Bond land See Bonding area.

Bond schedule The values of the bonding machine

parameters used when adjusting for bonding. For example,

in ultrasonic bonding, the values of the bonding force,

time, and ultrasonic power.

Bond separation The distance between the attachment

point of the ﬁrst and second bonds of a wire bond.

Bond site The portion of the bonding areas where the

actual bonding took place (see Bonding area).

Bond strength In wire bonding, the pull force at rupture

of the bond interface measured in the unit gram-force.

Bond surface See Bonding area.

Bond-to-bond distance The distance measured from the

bonding site on the die to the bond impression on the post,

substrate land, or ﬁngers, which must be bridged by a

bonding wire or ribbon.

Bond-to-chip distance In beam lead bonding the distance

from the heel of the bond to the component.

Bond tool The instrument used to position the lead(s)

over the desired bonding area and impart sufficient energy

to the lead(s) to form a bond.

Bondability Those surface characteristics and conditions

of cleanliness of a bonding area which must exist in order

to provide a capability for successfully bonding an inter-

connection material by one of several methods, such as

ultrasonic or thermo-compression wire bonding.

Bonding, die Attaching the semiconductor chip to the

substrate, either with an epoxy, eutectic or solder alloy.

Bonding area The area, deﬁned by the extent of a metal-

lization land or the top surface of the terminal, to which a

lead is or will be bonded.

Bonding island Same as Bonding land.

Bonding land A metallized area at the end of a thin

metallic strip to which a connection is to be made.

Bonding wire Fine gold or aluminum wire for making

electrical connections in hybrid circuits between various

bonding lands on the semiconductor device substrate and

device terminals or substrate lands.

BTAB The acronym for tape automated bonding when

the raised bump for each bond site is prepared on the tape

material as opposed to the bump being on the component.

Bugging height The distance between the hybrid sub-

strate and the lower surface of the beam lead device which

occurs because of deformation of beam leads during beam

lead bonding.

Chip The uncased and normally leadless form of an elec-

tronic component part, either passive or active, discrete or

integrated. chip-and-wire. A hybrid technology employing

face-up-bonded chip devices exclusively, interconnected to

the substrate conventionally (i.e. by ﬂying wires).

Chip carrier A special type of enclosure or package used

to house a semiconductor device or a hybrid microcircuit

which has metallized electrical terminations around its

perimeter rather than an extended lead frame or plug-in

pins.

Chopped bond Those bonds with excessive deformation

such that the strength of the bond is greatly reduced.

Co-ﬁring Processing the thick-ﬁlm conductors and resis-

tors through the ﬁring cycle at the same time.

Contact angle The angle made between the bonding

material and the bonding land.

Coplanar leads (ﬂat leads) Ribbon-type leads extending

from the sides of the circuit package, all lying in the same

plane.

Cratering Defect in which a portion of chip under the

ultrasonic bond is torn loose, leaving a pit, by excessive

amount of energy transmitted through the wire bond.

Die An uncased discrete or integrated device obtained

from a semiconductor wafer (see Chip).

Die bond Attachment of a die or chip to the hybrid sub-

strate.

Dielectric Materials that do not conduct electricity and

that are used for making capacitors, for insulating conduc-

tors (as in crossover and multilayer circuits), and for encap-

sulating circuits.

Digital circuits Applied normally for switching applica-

tions where the output of the circuit normally assumes one

or two states (binary operation); however, three state opera-

tion is possible.

Direct contact A contact made to the semiconductor die

when the wire is bonded directly over the part to be elec-

trically connected, as opposed to the expanded contact.

Doping The addition of an impurity to a semiconductor

to alter its conductivity.

Face bonding The opposite of back bonding. A face

bonded semiconductor chip is one that has its circuitry side

facing the substrate. Flip-chip and beam lead bonding are

the two common face bonding methods.

Field trimming Trimming of a resistor to set an output

voltage, current, etc.

December 1989 IPC-D-859