IPC-D-859.pdf - 第17页

one capacitor for not more than ﬁve logic devices and one for no more than two memory devices. 4. Minimize the impedance and radiation loop of the decoupling capacitor by keeping capacitor leads as short as possible, and…

3.4.4 Power Distribution Considerations Power distri-

bution is important in the design of a multilayer hybrid cir-

cuit. The grounding scheme, as a part of the distribution

system, provides not only a DC power return, but also pro-

vides an RF return plane for digital logic to be referenced.

In a typical multilayer design, a combination power/ground

plane is screened directly on the substrate. Vias for the

power and ground connections are often made larger than

the vias for signal interconnection because the power and

ground connection vias carry more power and they traverse

more layers. Above this are alternate layers of dielectric

and interconnect metallization.

The top layer contains all device I/O bonding lands and the

substrate I/O lands. If space permits, this layer may also

contain some interconnections.

Metallization lands are provided for physical attachment of

the integrated circuit chips. These lands are normally con-

nected to ground or a voltage supply. Eight metallization

layers are generally considered to be a reasonable maxi-

mum. The base metal in coated metal-core substrates may

be utilized as a ground plane that is contacted directly by

printing a circuit directly over a via through the coating.

The following items should be taken into consideration:

1. Maintain a lower RF impedance throughout the DC

power distribution. An improperly designed ground

can result in RF emissions as a result of radiated ﬁeld

gradients developed across the uneven circuit imped-

ance, and its inability of decoupling capacitors to effi-

ciently reduce the EMI.

2. Decouple the power distribution at the hybrid circuit

connector using a 1.0 to a 10.0 microfarad tantalum

capacitor.

3. A ceramic capacitor of approximately 0.01 microfarads

should be connected across VCC or source voltage;

IPC-859-3-2

Figure 3–2 Nominal thick ﬁlm conductor and land dimensional constraints (see Table 3–1)

TOP HAT 

CONFIGURATION

CONDUCTOR

0.91

[0.036]

0.51

[0.020]



0.32

0.0125

0.41

[0.016]

0.32

[0.0125]

0.51

[0.020]

0.32

[0.0125]

0.51

[0.020]



Bonding

Pad

0.51

[0.020]



EDGE OF 

SUBSTRATE

LEAD

DIMENSIONS

IN mm [inches]

IPC-D-859 December 1989

one capacitor for not more than ﬁve logic devices and

one for no more than two memory devices.

4. Minimize the impedance and radiation loop of the

decoupling capacitor by keeping capacitor leads as

short as possible, and locating them adjacent to the

integrated circuit.

The power and ground planes are solid when using the

gold system.

The power and ground planes are typically gridded with

0.4 mm [0.015 inch] conductors, and 0.25 mm [0.010 inch]

spaces as shown in Figure 3–10 when using the copper

system.

In digital power distribution schemes, the grounding and

power should be designed ﬁrst, not last, as is typically

done. All interfacing, including power, should be routed to

a single reference edge, or area. Avoid opposing end inter-

connections. At the interconnection reference edge, all

ground structures are to be made as heavy as possible.

IPC-859-3-3

Figure 3–3 Special ﬁneline conductor dimensions

(nominal) and positioning constraints (see Table 3–1)

EDGE OF 

SUBSTRATE

NOTE: A conductor adjacent to the edge of the substrate must be a minimum 

of 0.25 mm [0.010 inch] wide and at least 0.25 mm [0.010inch] in from the edge.

0.32 [0.0125]

0.25 [0.010] min. (see note)

0.25 [0.010] min. 

(see note)

0.25 

[0.010] 



0.25 

[0.010] 



0.32 

[0.0125]

IPC-859-3-4

Figure 3–4 Nominal thick ﬁlm crossover dimensions

(see Table 3–1)

0.38

[0.015]

0.38

[0.015]

0.38

[0.015]

0.32

[0.025]

0.76 [0.030]

0.38 [0.015]

CROSSOVER

DIELECTRIC

LOWER LEVEL

CONDUCTOR

UPPER LEVEL

CONDUCTOR

SEE NOTE

NOTE:

This conductor

dimension should

be at least 0.13 mm

[0.005 inch] wider 

than the width of 

the upper conductor.

SEE 

NOTE

IPC-859-3-5

Figure 3–5 Transmission line multilayer hybrid circuit

construction

IPC-859-3-6

Figure 3–6 Typical microwave circuit types

December 1989 IPC-D-859

The shortest possible conductor length should be used

between devices. The hybrid circuit should be separated

into areas for high, medium, and low frequency circuits.

3.4.5 Circuit Type Considerations

3.4.5.1 Digital Circuits

Digital circuits are composed of

electronic components that can provide state information (1

or 0), as a function of the performance of the overall cir-

cuit. Normally, logic integrated circuits are used to perform

this function; however, discrete components may also be

used sometimes to provide digital responses.

Integrated circuit devices use a variety of logic families.

Each family has its own parameters regarding the speed of

the digital transmission, as well as the temperature rise

characteristics necessary to provide the performance. In

general, a single board usually uses the same logic family

in order to facilitate a single set of design rules for conduc-

tor length for signal driving restrictions. Some of the more

common logic families are:

• TTL—Transistor Transistor Logic

• MOS—Metal Oxide Semiconductor Logic

• CMOS—Complimentary Metal Oxide Semiconductor

Logic

• ECL—Emitter Coupled Logic

• The following guidelines should be used on all logic

designs to improve the testability of the multilayer

printed board assembly.

1. Connect the set, clear, or reset of all ﬂip-ﬂops to reset

terms. Power up reset is ideal. See Figure 3–11.

2. Connect the clear or master reset of counters to reset

terms or provide preset logic. See Figure 3–12.

3. Provide a method to disable free-running oscillators,

and provide a pin-out to an unused I/O on the oscilla-

tor clock line.

4. Provide outputs to unused I/O pins for feedback or

‘‘deep’’ logic loops. This also applies for serial logic.

5. Keep direct output control, wherever possible, on all

LSI devices to enhance their testability.

6. Provide jumper lines from the delay line clock circuits

to unused I/O pins, so that intermediate clocks may be

controlled.

IPC-859-3-7

Figure 3–7 Stripline electric ﬁeld

▼

TYPICAL PARAMETERS

h = 0.635mm [0.025"]

w = 0.061mm [0.0024"]

t = 0.00635mm [0.00025"]

Er = 10 (Al O )

Z = 50

EEFF = 6.8

▼

Electric 

Field Lines

Conducting 

Ground Plane

Dielectric

Substrate

Conducting 

Strip

Ω

▼

IPC-859-3-8

Figure 3–8 Crossover capacitance

Shaded Area

Indicates Crossover

▼

IPC-859-3-9

Figure 3–9 Example of parallel line coupling capacitance

calculation

▼

1 3

▼

C Total = 6.7 x 10 = 6.7 x 10

}

pF)(

n=1

{

-4 -4

IPC-D-859 December 1989