IPC-D-859.pdf - 第35页

Depending upon the end use of the hybrid, the load-life characteristics of the resistors are of considerable impor- tance. Thick-ﬁlm chip resistors are available in standard values and tolerances from a size of 1.27 x 1.…

the remaining die will perform, it will serve as an indica-

tion of the electrical performance and the possible yield

level that can be expected during the further use of the

device in a hybrid. It will also help to identify defective

lots.

3.8.11.2 Transistors/Diodes (Active Devices) The same

considerations apply to discrete semiconductors as for inte-

grated circuits. However, in addition, there are the further

implications of diode polarity and die attachment.

3.8.11.2.1 Diode Polarity Most diodes can be obtained

with the anode/cathode at either side of the chip. Therefore,

the polarity of the wire bond surface of the chip must be

identiﬁed.

3.8.11.2.2 Die Attachment Unlike most integrated cir-

cuits that are epoxy-mounted to the hybrid substrate, cer-

tain devices may require eutectic attachment to the sub-

strate. When the attachment is to be eutectic, the device

must be obtained with gold backing.

3.8.11.3 Passive Devices Passive devices are those

other than integrated circuits or semiconductor devices

(such as capacitors, resistors, inductors, thermistors, etc.),

that are procured as separately manufactured components.

They can also be integrally deposited on the substrate.

Passive devices typically require fewer electrical connec-

tions than do active devices. When passive devices have

been separately manufactured, there are two major methods

of mounting: (1) using a non-conductive adhesive and wire

bonding the electrical connection, and (2) using either con-

ductive adhesives or solder (solder will require a higher

temperature than the adhesive but may be processed

faster).

A decision as to the attachment method must be made prior

to specifying the termination material used on the passive

device.

3.8.11.3.1 Capacitors Integrally-deposited capacitors, in

thick-ﬁlm hybrid circuits, are used for special applications.

However, present state-of-the-art process techniques and

compatible dielectrics impose serious limitations in terms

of tolerance, capacitance value and dissipation factor con-

trol. Therefore, in most cases, add-on chip capacitors are

employed in hybrid circuits due to the fact that optimum

characteristics are usually achieved by unique material sys-

tems, fabrication techniques, and geometries.

Chip-capacitor devices are available in silicon, ceramic

wafer, multilayer ceramic, or ribbon leaded conﬁgurations.

Also, they are available in a wide range of capacitances,

voltage ratings, and dielectric materials.

The hybrid-circuit designer’s choice of chip capacitors will

primarily be in the area of ceramic dielectrics with the

more commonly offered formulations having their charac-

teristics standardized in both military and commercial stan-

dards.

A. The designer is cautioned that speciﬁcations and stan-

dards are usually only a basic framework, as the char-

acterization data is often obtained at very low frequen-

cies.

B. Actual capacitor performance and behavior under vari-

ous circuit conditions and high frequencies may vary

considerably from that of standard test formats and may

vary from one maker to another due to their use of pro-

prietary ceramic formulations.

C. The high dielectric-constant ceramic formulations usu-

ally have non-linear temperature coefficients. They

exhibit frequency and voltage coefficients that often are

not speciﬁed in vendor data sheets.

D. Under certain operating conditions, the very high

dielectric constant ceramic formulations may result in

the actual capacitance value dropping to 10 percent of

the rated value.

E. Consultation with potential vendors and testing under

simulated operating conditions are recommended when

selecting a capacitor for a given application.

F. For those applications involving very-high-speed digi-

tal circuits, VHF/UHF circuits, and microwave analog

circuits, important concerns will be focused on dissipa-

tion factor (dielectric dependent) and self-resonant fre-

quency (electrode-size and conﬁguration dependent)

characteristics.

The use of variable-value capacitors is discouraged since

they present mounting problems and are not readily avail-

able for hybrid usage.

3.8.11.3.2 Resistors Resistor choice is based upon a

number of electrical, thermal, and processing capability

considerations. Therefore, integrally-deposited thick-ﬁlm

resistors are frequently used if the characteristics of the

resistive ﬁlms meet circuit requirements for precision, tem-

perature stability, etc.

The capability to trim-to-value is usually required. If

requirements cannot be met with trimmed integrally-

deposited resistors, add-on chip resistors are available in

both discrete and network conﬁgurations.

The circuit designer must carefully specify the desired

resistor characteristics, such as ohmic value, tolerance,

temperature range/coefficient, and power dissipation. How-

ever, the hybrid- circuit designer has the additional prob-

lem of determining what temperatures the resistor may

actually experience caused by heat induced by neighboring

components and the available thermal paths out of the

package.

IPC-D-859 December 1989

Depending upon the end use of the hybrid, the load-life

characteristics of the resistors are of considerable impor-

tance.

Thick-ﬁlm chip resistors are available in standard values

and tolerances from a size of 1.27 x 1.27 x 0.51 mm [0.050

x 0.050 x 0.020 inch] at 0.1 W dissipation capability to

increased dimensions in proportion to higher power dissi-

pation capabilities.

Thin-ﬁlm (tantalum nitride and nickel-chromium) chip

resistors are available in a wide variety of networks or dis-

crete values. Thin-ﬁlm resistors can be obtained in several

conﬁgurations with sizes from 0.93 x 0.43 x 0.28 mm

[0.017 x 0.017 x 0.011 inch] for a single-value resistor.

Some conﬁgurations include several different values on a

larger chip.

3.8.11.3.3 Inductors The inductor has historically pre-

sented a size problem to the hybrid designer and has con-

tributed the least to chip format miniaturization. The etched

thin-ﬁlm spiral or the screened thick-ﬁlm spiral have been

used for inductors to some degree, but they are limited in

terms of quality factor (‘‘Q’’) and inductance range.

The primary concern when selecting a chip inductor is its

physical size, as height restrictions of the hybrid package

will limit the type and range of inductors that can be used.

Miniature wire-wound inductors are available in sizes of

2.67 x 2.79 x 1.65 mm [0.105 x 0.110 x 0.065 inch] in a

range of from 0.01 to 10,000 microhenries in standard val-

ues.

3.8.11.3.4 Networks (Arrays) Multiple capacitors on a

chip and multiple resistors on a chip are becoming avail-

able in a wide variety of conﬁgurations that serve a num-

ber of circuit and assembly cost-reduction requirements.

Combination multiple resistor/capacitor networks on a chip

area also available. In most cases, these are custom compo-

nents that require close collaboration with the potential

vendor(s).

3.8.11.4 Thermal Derating During the design/selection

phase, the thermal limitations imposed should be noted.

Unlike packaged devices, the hybrid thermal environment

must be calculated/measured for each application, since

packaging density/mounting will determine the thermal rise

of the device.

In addition, each particular family of devices has its own

unique derating considerations. Derating guidelines for

integrated circuits, semiconductors, capacitors, resistors

and inductors are summarized in Table 3–16.

3.8.11.5 Electrical Derating All hybrid circuit parts

should conform to the derating guidelines speciﬁed in

Table 3–16. In addition, program guidelines may require

more conservative derating.

3.8.11.6 Preconditioning Evaluations Hybrid compo-

nents designed for military and other high reliability appli-

cations must be capable of surviving the preconditioning/

screening schedule speciﬁed in MIL-M-38510 and MIL-

STD-883.

4.0 COMPONENT MOUNTING AND ATTACHMENT

The mounting and attachment of components play an

important role in the design of a hybrid circuit. In addition

to their obvious effect on component density and conduc-

tor routing, these aspects of design also impact assembly,

solder joint integrity, repairability and testing. Therefore, it

is important that the design reﬂect appropriate tradeoffs

that recognize these and other signiﬁcant manufacturing

considerations.

As a minimum, component mounting and attachment

should be based on the following considerations:

• Electrical and tolerance requirements of the circuit

design

• Environmental requirements

• Selection of standard electronic components, terminals

and connectors.

• Size and weight within space limits

• Minimize heat generation and heat dissipation problems

• Manufacturing, processing, and handling requirements

• Contractual requirements

• Serviceability requirements

• Automatic placement requirements, when this method of

assembly is to be used

• Test method to be employed before, during, and after

assembly

• Field repair and maintenance considerations

4.1 General Requirements

4.1.1 Component Placement

The number of compo-

nents that can be put into one hybrid and their placement is

constrained by the package dimensions, heat-transfer capa-

bility, and considerations of manufacturing yield, pin-out

complexity, and testability.

4.1.2 Orientation Designs intended to have components

mounted horizontally should have the major axis of the

components parallel to grid lines (board edge), and prefer-

ably with the major axis parallel to the direction of cooling

air ﬂow. In addition, the components should be mounted

mutually parallel or perpendicular to provide an orderly

appearance. Pin 1 of all chip carriers should be indicated

on the bonding land of the top layer by extending the pin-

one feature of the footprint. In addition, appropriate corner

marks should also be added to the top layer to assist in

assembling and inspecting the carriers.

December 1989 IPC-D-859

Table 3–16 Derating Guidelines

Substrate Part Types

Maximum Rated Derating Factor

Operating Junction

Temperature (Tj)

Power

Stress Voltage/Current Stress

Design Goal

(%)

Absolute

Maximum (%)

Design Goal

(%)

Absolute

Maximum (%)

Design Goal

Hot Spot (°C

Allowable)

Absolute

Maximum

Hot Spot

(°C Rated)

Resistor, thick/thin ﬁlm 25 50 — 80 N/A N/A

Resistor, ﬁlm chip 50 80 — 80 N/A N/A

Capacitor, ceramic ﬁlm chip

N/A N/A 50 80 N/A N/A

Capacitor, tantalum ﬁlm chip

NA N/A 50 80 N/A N/A

Inductor, ﬁlm chip — — — 60 I

AVE

80 I

110 125

Diode, chip (general

purpose, zener, microwave)

— — — 60 PIV

60 I

110 135

Transistor, chip

(bipolar & FET)

———60V

CEO

60 V

EBP

60 V

60 I

110 135

Integrated Circuits

Digital Bipolar — — — 75

FAN-OUT

75 I

SINK

95 110

Digital MOS (CMOS) — — — 75

FAN-OUT

75 I

SINK

75 I

85 110

Linear — 90 PSV — 75 I

95 115

Bipolar TTL Memories — — — 75 I

105 125

MOS Memories, Static

or Dynamic

———75I

95–Static

85–Dynamic

105–Static

100–Dynamic

1. For repetitive pulse applications, determine the average power (P

AVE

) as follows:

AVE

)=E

/R x t/T

where: E

/R = peak power

t = pulse duration

T = duty cycle

2. Voltages must never be applied in reverse of the normal polarization of a polarized capacitor.

3. Maximum junction temperature ratings for all semiconductors and integrated circuits are assumed to be greater than or equal to

the maximum operating temperature required of the device.

4. Legend

FAN-OUT

FET

AVE

SINK

PIV

Number of input loads driven

Field effects transistors

Average current

Base current

Collector current

Forward current

Gate current

Load current

Source current

Sink current

Zener (maximum) current

Peak inverse voltage

PSV

TTL

CEO

DIF

EBO

Power supply voltage

Transistor-Transistor logic

Collector-to-emitter voltage with base open

Differential input voltage (deﬁned as applied

input voltage swing vs. manufacturer’s speciﬁed

input swing)

Emitter-to-base voltage with collector open

Gate-to-drain voltage

Gate-to-source voltage

Peak voltage

Voltage supply

IPC-D-859 December 1989