IPC-D-859.pdf - 第16页

3.4.4 Power Distribution Considerations Power distri- bution is important in the design of a multilayer hybrid cir- cuit. The grounding scheme, as a part of the distribution system, provides not only a DC power return, b…

Plane sequences should be arranged so that the signal lay-

ers are symmetrical about the ground or voltage plane. This

may be accomplished several ways provided that any adja-

cent signal layers, not separated by a ground or voltage

plane must have their key axes running perpendicular to

each other. (see Figure 3–1).

DC power and ground planes also function as AC reference

planes. Power and ground connector pins should be evenly

distributed along the edge of the board for AC reference.

3.4.3.1 Capacitance Considerations The capacitance

associated with a single crossover (see Figure 3–8) is very

small and is typically a fraction of a picofarad. As the

number of crossovers per unit length increases, the intrin-

sic capacitance of the transmission line also increases. The

crossover lumped capacitance adds to the intrinsic line

capacitance. Crossover capacitance may be approximated:

C(pF)=5.72 E

(l + 0.8h)

(W + 0.8h)

provided that l ≥ 0.5h

W ≥ 0.5h

Where:

= dielectric constant

h = dielectric thickness between crossovers

(mm)

l = length (mm)

W = width (mm)

The distributed coupling capacitance between two parallel

conductors on the same layer (see Figure 3–9), assuming

0.015 mm [0.0006 inch] print thickness, is given by

∑ 6.7x10

–4

n = 1

Where: l

= length of parallelism between the conduc-

tors

for separation d

= perpendicular distance between

the conductors

The above equation is a ﬁrst order approximation which

disregards capacitance contributed by all other conductors

distributed across the entire substrate. It is assumed that the

ﬁrst order contributions constitute 90% or more of the cou-

pling capacitance, and that coupling between adjacent con-

ductors is the prime concern.

Circuit design shall specify the allowable capacitances

from which the required spacing and maximum parallelism

shall be determined.

Table 3–1 Dimensional Constraints for Thick-Film Conductors and Lands

Conductor and Land Sizes and Spacing

Minimum

Dimension

mm [inch]

Nominal

Dimension

mm [inch]

Maximum

Dimension

mm [inch] Figure Item

Conductor to edge of substrate for conductors

≤0.38 mm [0.015 inch]

0.25 [0.010] 0.51 [0.020] None 3–2

Conductor to edge of substrate for conductors

>0.38 mm [0.015 inch]

0.25 [0.010] 0.32 [0.0125] None 3–2

Exit bonding lands (width and length) 0.25 [0.010] 0.32 [0.0125] None 3–2

Wire bonding lands (width and length—one or two

wires on same land) (preferred)

0.25 [0.010] 0.32 [0.0125] None 3–2

Wire bonding lands (width and length—one wire per

land (special)

0.25 [0.010] 0.32 [0.0125] None 3–3

Conductor width (preferred) 0.25 [0.010] 0.51 [0.020] None 3–2

Conductor width (special) 0.13 [0.005] 0.25 [0.010] None 3–3

Conductor-to-conductor spacing (preferred) 0.25 [0.010] 0.51 [0.020] None 3–2

Conductor-to-conductor spacing (special) 0.13 [0.005] 0.25 [0.010] None 3–3

Conductor-to-resistor spacing (on untrimmed

side of resistor)

0.25 [0.010] 0.38 [0.015] None 3–4

Conductor-to-resistor spacing (on trimmed side of

resistor)

0.38 [0.015] 0.51 [0.020] None 3–4

Conductor-to-resistor spacing, top-hat conﬁguration 0.76 [0.030] 0.89 [0.035] None 3–2

Upper and lower conductor widths at crossover junc-

tion

0.25 [0.010] 0.38 [0.015] None 3–4

Crossover conductor-to-connecting-conductor

overlap-length

0.25 [0.010] 0.32 [0.0125] None 3–4

Conductor crossover dielectric overlap 0.25 [0.010] 0.38 [0.015] None 3–4

Dielectric to resistor spacing 0.51 [0.020] 0.51 [0.020] None 3–4

December 1989 IPC-D-859

3.4.4 Power Distribution Considerations Power distri-

bution is important in the design of a multilayer hybrid cir-

cuit. The grounding scheme, as a part of the distribution

system, provides not only a DC power return, but also pro-

vides an RF return plane for digital logic to be referenced.

In a typical multilayer design, a combination power/ground

plane is screened directly on the substrate. Vias for the

power and ground connections are often made larger than

the vias for signal interconnection because the power and

ground connection vias carry more power and they traverse

more layers. Above this are alternate layers of dielectric

and interconnect metallization.

The top layer contains all device I/O bonding lands and the

substrate I/O lands. If space permits, this layer may also

contain some interconnections.

Metallization lands are provided for physical attachment of

the integrated circuit chips. These lands are normally con-

nected to ground or a voltage supply. Eight metallization

layers are generally considered to be a reasonable maxi-

mum. The base metal in coated metal-core substrates may

be utilized as a ground plane that is contacted directly by

printing a circuit directly over a via through the coating.

The following items should be taken into consideration:

1. Maintain a lower RF impedance throughout the DC

power distribution. An improperly designed ground

can result in RF emissions as a result of radiated ﬁeld

gradients developed across the uneven circuit imped-

ance, and its inability of decoupling capacitors to effi-

ciently reduce the EMI.

2. Decouple the power distribution at the hybrid circuit

connector using a 1.0 to a 10.0 microfarad tantalum

capacitor.

3. A ceramic capacitor of approximately 0.01 microfarads

should be connected across VCC or source voltage;

IPC-859-3-2

Figure 3–2 Nominal thick ﬁlm conductor and land dimensional constraints (see Table 3–1)

TOP HAT 

CONFIGURATION

CONDUCTOR

0.91

[0.036]

0.51

[0.020]



0.32

0.0125

0.41

[0.016]

0.32

[0.0125]

0.51

[0.020]

0.32

[0.0125]

0.51

[0.020]



Bonding

Pad

0.51

[0.020]



EDGE OF 

SUBSTRATE

LEAD

DIMENSIONS

IN mm [inches]

IPC-D-859 December 1989

one capacitor for not more than ﬁve logic devices and

one for no more than two memory devices.

4. Minimize the impedance and radiation loop of the

decoupling capacitor by keeping capacitor leads as

short as possible, and locating them adjacent to the

integrated circuit.

The power and ground planes are solid when using the

gold system.

The power and ground planes are typically gridded with

0.4 mm [0.015 inch] conductors, and 0.25 mm [0.010 inch]

spaces as shown in Figure 3–10 when using the copper

system.

In digital power distribution schemes, the grounding and

power should be designed ﬁrst, not last, as is typically

done. All interfacing, including power, should be routed to

a single reference edge, or area. Avoid opposing end inter-

connections. At the interconnection reference edge, all

ground structures are to be made as heavy as possible.

IPC-859-3-3

Figure 3–3 Special ﬁneline conductor dimensions

(nominal) and positioning constraints (see Table 3–1)

EDGE OF 

SUBSTRATE

NOTE: A conductor adjacent to the edge of the substrate must be a minimum 

of 0.25 mm [0.010 inch] wide and at least 0.25 mm [0.010inch] in from the edge.

0.32 [0.0125]

0.25 [0.010] min. (see note)

0.25 [0.010] min. 

(see note)

0.25 

[0.010] 



0.25 

[0.010] 



0.32 

[0.0125]

IPC-859-3-4

Figure 3–4 Nominal thick ﬁlm crossover dimensions

(see Table 3–1)

0.38

[0.015]

0.38

[0.015]

0.38

[0.015]

0.32

[0.025]

0.76 [0.030]

0.38 [0.015]

CROSSOVER

DIELECTRIC

LOWER LEVEL

CONDUCTOR

UPPER LEVEL

CONDUCTOR

SEE NOTE

NOTE:

This conductor

dimension should

be at least 0.13 mm

[0.005 inch] wider 

than the width of 

the upper conductor.

SEE 

NOTE

IPC-859-3-5

Figure 3–5 Transmission line multilayer hybrid circuit

construction

IPC-859-3-6

Figure 3–6 Typical microwave circuit types

December 1989 IPC-D-859