IPC-D-859.pdf - 第5页

Table of Contents 1.0 Scope ........................................................................ 1 1.1 Purpose .............................................................. 1 1.2 Classification.......................…

100%1 / 88
Acknowledgment
As with all IPC documents, this
standard is possible only because a
large number of people volunteered
to share their time and expertise in
producing it. While the principle
members of the IPC Hybrid Design
Task Group are shown below, it is
not possible to include the names of
all those who assisted in developing
this standard. To each of them, the
members of the IPC extend their
gratitude.
Hybrid & Related
Technologies Committee
Hybrid Design Task Group Technical Liaison of the IPC
Board of Directors
Chairman
Bob Lomerson
General Dynamics
Chairman
Richard E. Park, Jr.
Raytheon
Gene Hendrickson
Tektronix
Hybrid Design Task Group
F.E. Bader, Bell Laboratories
J. Barton, Dept. of Defense
D. Benezra, Boeing Electronics Co.
S.T. Bora, Smiths Industries
P. Boudreau, Hughes Aircraft Co.
J. Carow, Unisys Corp.
Dr. R. Castonguay, Hicks & Otis
Prints Inc.
S. Clark, Bendix Oceanics Division
J.R. Dinitto, Electro Films Inc.
C.J. Dumas, Methode Electronics Inc.
R.E. Egloff, Acheson Colloids Co.
S. Ethridge, Hughes Aircraft Co.
J. Fjelstad, J.C. Fjelstad & Associates
M. Furukawa, Mitsui Toatsu
Chemicals Inc.
K.J. Gainor, Texas Instruments, Inc.
E.C. Galgoci, Shell Development Co.
S. Gazit, Rogers Corp.
G. Ginsberg, Component Data
Associates
R. Glaessgen, Coates Circuit
Products/USA
W.J. Greig, Wm. J. Greig Assoc. Inc.
B. Gutek, Dow Corning Corp.
D.H. Hundrieser, Northern Telecom
S. Jain, Climax Specialty Metals
M.P. Kalliat, AT&T Bell Laboratories
G.W. Kenealey, Control Data Corp.
H. King, DIT MCO International
G. Kromholtz, Eldec Corp.
B. Leider, Magnavox Electronics
Systems
G.F. Love, Martin-Marietta Missile
Systems
B. Mahler, Ohmega Technologies,
Inc.
R. Maki,3M Co.
M. Marken, Texas Instruments, Inc.
J. Mc Donald, Rensselaer Polytechnic
Inst.
J. Mislak, Dept. of Defense
J. Mitchell, E.I. DuPont De Nemours
& Co.
R.B. Nami, Palomar Systems
L.J. Nielsen, Raytheon Co.
C.T. Ray, Fairchild
L. Razzetti, Westinghouse Electric
Corp.
M.A. Savrin, Kulicke & Soffa
Industries Inc.
D. Seck, DIT MCO International
J.P. Smigie
Lt. W. Stewart, Rome Air
Development Center
T. Suppelsa, Motorola Inc.
J.R. Thome, Motorola Inc.
J.S. Tucker, Unisys Corp.
F.W. Verdi, AT&T Bell Laboratories
W. Vitriol, Hughes Aircraft Co.
T.M. White, Boeing Electronics Co.
C.A. Willey, MSN-Products (PTY)
Ltd.
Dr. A. Wilson, Texas Instruments Inc.
G. Yau, Unisys Corp.
N.S. Yokoro, Hughes Aircraft Co.
E. Zimmerman, Boeing
Special Note of Appreciation
A special note of appreciation goes to
the following individuals who met
repeatedly to help develop this
document:
Tracy Merlin, Unisys
George Smith, Trace
Thomas Newton, Norplex/Oak
Les Hymes, GE
George Harman, National Bureau
of Standards
Dennis Fritz, Mac Dermid
Don Dinella, AT&T
Al Cafferty, NCR
Winston Veazey, TI
Richard Douglas, Douglas
& Associates
Robert Lomerson, General Dynamics
Richard Park Jr., Raytheon
December 1989 IPC-D-859
ii
Table of Contents
1.0 Scope........................................................................ 1
1.1 Purpose .............................................................. 1
1.2 Classification...................................................... 1
1.2.1 Circuit Type....................................................... 1
1.3 Presentation........................................................ 1
2.0 Applicable Documents ........................................... 1
2.1 IPC..................................................................... 1
2.2 Government Documents.................................... 2
2.2.1 Military .............................................................. 2
2.2.2 Federal ............................................................... 2
2.3 Other Publications............................................. 2
2.3.1 ASTM ................................................................ 2
2.3.2 EIA..................................................................... 2
3.0 Design Considerations........................................... 2
3.1 Terms and Definitions ....................................... 2
3.2
Design Features................................................. 6
3.3
Documentation Package.................................... 6
3.3.1
Master Drawing Package .................................. 6
3.3.2
Viewing.............................................................. 7
3.3.3
Location Dimensioning..................................... 7
3.3.4
Hole Location Tolerance................................... 7
3.3.5
Processing Allowances...................................... 7
3.3.6
Datums............................................................... 7
3.4
Electrical Requirement Considerations............. 7
3.4.1
Conductor Thickness and Width....................... 7
3.4.2
Electrical clearance............................................ 7
3.4.3 Impedance/Capacitance Control
Considerations ................................................... 7
3.4.4
Power Distribution Considerations................. 10
3.4.5
Circuit Type Considerations............................ 12
3.5
Thermal Requirement Considerations ............ 14
3.5.1
Material Selection............................................ 16
3.5.2
Substrate Dimensions...................................... 16
3.5.3
General Guidelines.......................................... 16
3.5.4
Heat Dissipation Calculations......................... 16
3.5.5
Thermal Matching........................................... 17
3.6
Mechanical Requirement Considerations ....... 17
3.6.1
Camber............................................................. 17
3.6.2
Support............................................................. 17
3.6.3
Shock and Vibration........................................ 18
3.7
Test Requirement Considerations ................... 18
3.7.1
Hybrid Circuit Layout Design ........................ 18
3.8
Materials .......................................................... 18
3.8.1
Substrates......................................................... 19
3.8.2
Conductive Materials ...................................... 20
3.8.3 Resistive Materials .......................................... 21
3.8.4 Dielectric Materials......................................... 22
3.8.5 Metallic Platings and Coatings....................... 22
3.8.6 Organic Protective Coatings ........................... 23
3.8.7 Solder and Flux............................................... 23
3.8.8 Attachment Materials ...................................... 23
3.8.9 Chip to Substrate Interconnect........................ 25
3.8.10 Tape Automated Bonding (TAB).................... 26
3.8.11 Components..................................................... 27
4.0 Component Mounting and Attachment .............. 29
4.1 General Requirements..................................... 29
4.1.1 Component Placement..................................... 29
4.1.2 Orientation....................................................... 29
4.1.3 Accessibility .................................................... 31
4.1.4 Boundaries....................................................... 31
4.1.5 Chip Carrier Centering.................................... 31
4.1.6 Mounting Components Over Conductors....... 31
4.1.7 Clearances........................................................ 31
4.1.8 Physical Support.............................................. 31
4.1.9 Height Restriction............................................ 31
4.1.10 Heat Dissipation .............................................. 31
4.1.11 Stress Relief..................................................... 31
4.1.12
Automatic Assembly ....................................... 31
4.2
Surface-Mounted Leaded Components........... 32
4.2.1
Gull Wing (Flat-Pack) Components ............... 32
4.2.2
SO I/C’s........................................................... 32
4.2.3
Plastic Chip Carrier......................................... 32
4.2.4
Ribbon Lead Termination................................ 32
4.2.5
Round Lead Termination................................. 32
4.3
Surface Mount Leadless Components ............ 32
4.3.1
Chip Carriers ................................................... 32
4.3.2 Leadless Discrete Components
(Figure 4–12)................................................... 33
4.3.3
MELF............................................................... 33
4.4
Component Lead Sockets................................ 35
4.4.1
Integrated Circuit Sockets............................... 35
4.5
Connectors and Interconnects......................... 35
4.6
Special Wiring................................................. 37
4.6.1
Jumper Wires................................................... 37
4.6.2
Bus Bars .......................................................... 37
4.6.3
Flex Cable........................................................ 38
5.0 Hybrid Circuit Design Requirements.................. 39
5.1
Design/Fabrication Sequence.......................... 39
5.1.1
Schematic/Logic Diagram............................... 39
5.1.2
Parts List.......................................................... 39
5.1.3
End-product Requirements.............................. 39
December 1989 IPC-D-859
iii
5.1.4 Testing Requirements...................................... 39
5.1.5 Layout Concepts.............................................. 40
5.2 Substrate Geometries....................................... 42
5.2.1 Size and Shape ................................................ 42
5.2.2 Dimensions and Tolerances............................. 43
5.2.3 Datums............................................................. 43
5.2.4 Thickness Considerations................................ 43
5.2.5 Substrate Edges ............................................... 43
5.3 Circuit Features ............................................... 43
5.3.1 Conductors....................................................... 43
5.3.2 General Requirements for Lands and
Bond Lands...................................................... 45
5.3.3 Wire Bonds...................................................... 49
5.3.4 Resistors........................................................... 52
5.3.5 Vias .................................................................. 57
5.4 Coatings and Markings ................................... 58
5.4.1 Conformal Coatings ........................................ 58
5.4.2 Compatibility................................................... 58
5.4.3 Legends............................................................ 58
5.5 Artwork............................................................ 58
5.5.1 Artwork Masters.............................................. 59
5.5.2 Base Material................................................... 59
5.5.3 Accuracy.......................................................... 59
5.5.4 Pinholes............................................................ 60
5.5.5 Opaque Defects (Specks)................................ 60
5.5.6 Reproduction Conditions................................. 60
5.5.7 Packaging and Handling of Artwork
Masters............................................................. 60
5.6 Documentation................................................. 60
5.6.1 Master Drawing............................................... 60
5.6.2 Assembly Drawing.......................................... 61
5.6.3 Final Schematic/Logic..................................... 62
5.6.4 Final Bill of Material ...................................... 62
6.0 Quality Assurance................................................. 63
6.1 General............................................................. 63
6.2 Bare Board Testing.......................................... 63
6.2.1 Approaches ...................................................... 63
6.3 Design Considerations..................................... 63
6.3.1 Lands On Grid................................................. 63
6.3.2 Lands Off Grid ................................................ 63
6.3.3 Power-to-Ground Measurement...................... 63
6.4 Test Tapes ........................................................ 63
6.5 Test Circuitry................................................... 63
6.5.1 Quantity ........................................................... 63
6.5.2 Manufacturing Requirements.......................... 63
6.5.3 Identification.................................................... 63
6.5.4 Number of Layers ........................................... 64
6.5.5 Test Coupon Examples For Quality
Conformance Testing....................................... 64
6.5.6 Added Test Circuitry....................................... 65
IPC-D-859 December 1989
iv