IPC-D-859.pdf - 第36页

T able 3–16 Derating Guidelines Substrate Part T ypes Maximum Rated Derating Factor Operating Junction T emperature (Tj) 3 Power 1 Stress V oltage/Current Stress Design Goal (%) Absolute Maximum (%) Design Goal (%) Absol…

Depending upon the end use of the hybrid, the load-life

characteristics of the resistors are of considerable impor-

tance.

Thick-ﬁlm chip resistors are available in standard values

and tolerances from a size of 1.27 x 1.27 x 0.51 mm [0.050

x 0.050 x 0.020 inch] at 0.1 W dissipation capability to

increased dimensions in proportion to higher power dissi-

pation capabilities.

Thin-ﬁlm (tantalum nitride and nickel-chromium) chip

resistors are available in a wide variety of networks or dis-

crete values. Thin-ﬁlm resistors can be obtained in several

conﬁgurations with sizes from 0.93 x 0.43 x 0.28 mm

[0.017 x 0.017 x 0.011 inch] for a single-value resistor.

Some conﬁgurations include several different values on a

larger chip.

3.8.11.3.3 Inductors The inductor has historically pre-

sented a size problem to the hybrid designer and has con-

tributed the least to chip format miniaturization. The etched

thin-ﬁlm spiral or the screened thick-ﬁlm spiral have been

used for inductors to some degree, but they are limited in

terms of quality factor (‘‘Q’’) and inductance range.

The primary concern when selecting a chip inductor is its

physical size, as height restrictions of the hybrid package

will limit the type and range of inductors that can be used.

Miniature wire-wound inductors are available in sizes of

2.67 x 2.79 x 1.65 mm [0.105 x 0.110 x 0.065 inch] in a

range of from 0.01 to 10,000 microhenries in standard val-

ues.

3.8.11.3.4 Networks (Arrays) Multiple capacitors on a

chip and multiple resistors on a chip are becoming avail-

able in a wide variety of conﬁgurations that serve a num-

ber of circuit and assembly cost-reduction requirements.

Combination multiple resistor/capacitor networks on a chip

area also available. In most cases, these are custom compo-

nents that require close collaboration with the potential

vendor(s).

3.8.11.4 Thermal Derating During the design/selection

phase, the thermal limitations imposed should be noted.

Unlike packaged devices, the hybrid thermal environment

must be calculated/measured for each application, since

packaging density/mounting will determine the thermal rise

of the device.

In addition, each particular family of devices has its own

unique derating considerations. Derating guidelines for

integrated circuits, semiconductors, capacitors, resistors

and inductors are summarized in Table 3–16.

3.8.11.5 Electrical Derating All hybrid circuit parts

should conform to the derating guidelines speciﬁed in

Table 3–16. In addition, program guidelines may require

more conservative derating.

3.8.11.6 Preconditioning Evaluations Hybrid compo-

nents designed for military and other high reliability appli-

cations must be capable of surviving the preconditioning/

screening schedule speciﬁed in MIL-M-38510 and MIL-

STD-883.

4.0 COMPONENT MOUNTING AND ATTACHMENT

The mounting and attachment of components play an

important role in the design of a hybrid circuit. In addition

to their obvious effect on component density and conduc-

tor routing, these aspects of design also impact assembly,

solder joint integrity, repairability and testing. Therefore, it

is important that the design reﬂect appropriate tradeoffs

that recognize these and other signiﬁcant manufacturing

considerations.

As a minimum, component mounting and attachment

should be based on the following considerations:

• Electrical and tolerance requirements of the circuit

design

• Environmental requirements

• Selection of standard electronic components, terminals

and connectors.

• Size and weight within space limits

• Minimize heat generation and heat dissipation problems

• Manufacturing, processing, and handling requirements

• Contractual requirements

• Serviceability requirements

• Automatic placement requirements, when this method of

assembly is to be used

• Test method to be employed before, during, and after

assembly

• Field repair and maintenance considerations

4.1 General Requirements

4.1.1 Component Placement

The number of compo-

nents that can be put into one hybrid and their placement is

constrained by the package dimensions, heat-transfer capa-

bility, and considerations of manufacturing yield, pin-out

complexity, and testability.

4.1.2 Orientation Designs intended to have components

mounted horizontally should have the major axis of the

components parallel to grid lines (board edge), and prefer-

ably with the major axis parallel to the direction of cooling

air ﬂow. In addition, the components should be mounted

mutually parallel or perpendicular to provide an orderly

appearance. Pin 1 of all chip carriers should be indicated

on the bonding land of the top layer by extending the pin-

one feature of the footprint. In addition, appropriate corner

marks should also be added to the top layer to assist in

assembling and inspecting the carriers.

December 1989 IPC-D-859

Table 3–16 Derating Guidelines

Substrate Part Types

Maximum Rated Derating Factor

Operating Junction

Temperature (Tj)

Power

Stress Voltage/Current Stress

Design Goal

(%)

Absolute

Maximum (%)

Design Goal

(%)

Absolute

Maximum (%)

Design Goal

Hot Spot (°C

Allowable)

Absolute

Maximum

Hot Spot

(°C Rated)

Resistor, thick/thin ﬁlm 25 50 — 80 N/A N/A

Resistor, ﬁlm chip 50 80 — 80 N/A N/A

Capacitor, ceramic ﬁlm chip

N/A N/A 50 80 N/A N/A

Capacitor, tantalum ﬁlm chip

NA N/A 50 80 N/A N/A

Inductor, ﬁlm chip — — — 60 I

AVE

80 I

110 125

Diode, chip (general

purpose, zener, microwave)

— — — 60 PIV

60 I

110 135

Transistor, chip

(bipolar & FET)

———60V

CEO

60 V

EBP

60 V

60 I

110 135

Integrated Circuits

Digital Bipolar — — — 75

FAN-OUT

75 I

SINK

95 110

Digital MOS (CMOS) — — — 75

FAN-OUT

75 I

SINK

75 I

85 110

Linear — 90 PSV — 75 I

95 115

Bipolar TTL Memories — — — 75 I

105 125

MOS Memories, Static

or Dynamic

———75I

95–Static

85–Dynamic

105–Static

100–Dynamic

1. For repetitive pulse applications, determine the average power (P

AVE

) as follows:

AVE

)=E

/R x t/T

where: E

/R = peak power

t = pulse duration

T = duty cycle

2. Voltages must never be applied in reverse of the normal polarization of a polarized capacitor.

3. Maximum junction temperature ratings for all semiconductors and integrated circuits are assumed to be greater than or equal to

the maximum operating temperature required of the device.

4. Legend

FAN-OUT

FET

AVE

SINK

PIV

Number of input loads driven

Field effects transistors

Average current

Base current

Collector current

Forward current

Gate current

Load current

Source current

Sink current

Zener (maximum) current

Peak inverse voltage

PSV

TTL

CEO

DIF

EBO

Power supply voltage

Transistor-Transistor logic

Collector-to-emitter voltage with base open

Differential input voltage (deﬁned as applied

input voltage swing vs. manufacturer’s speciﬁed

input swing)

Emitter-to-base voltage with collector open

Gate-to-drain voltage

Gate-to-source voltage

Peak voltage

Voltage supply

IPC-D-859 December 1989

The corner marks may be located at all four corners in a

position slightly beyond the conﬁguration of the device as

shown in Figure 4–1.

Wherever possible, pin 1 of a chip carrier shall be identi-

ﬁed on the artwork by placing a small (approximately 0.25

mm [0.010 inch]) square adjacent to the footprint mounting

land for pin 1.

Orientation marks for all polarized discrete components

should be shown on the artwork. Cathodes of diodes and

the anode of polarized capacitors should be speciﬁed on the

assembly drawing.

4.1.3 Accessibility The placement of any component on

the circuit should not prevent the insertion or removal of

any hardware (tool clearance needed) used to mount or

repair/rework the assembly.

4.1.4 Boundaries The projection of the component on

the board should not extend over the edge of the substrate

or interfere with substrate mounting.

Unless otherwise detailed on the assembly drawing, the

substrate, edge is regarded as the extreme perimeter of the

assembly, beyond which no portion of the component is

allowed to extend. The designer shall prescribe the perim-

eter with due respects for maximum part body dimensions,

and the mounting provisions dictated by the circuit and

assembly documentation.

4.1.5 Chip Carrier Centering Chip carriers can be

placed on the solder paste using either manual or automatic

means. When placing the CC’s, alignment is critical with

the maximum misalignment being agreed upon between

user and vendor with due consideration for minimum sol-

der joint width, conductor clearance and the class of equip-

ment being produced.

4.1.6 Mounting Components Over Conductors When

bodies of components are mounted across more than one

conductor on Class B or Class C hybrid circuit assemblies,

the surface shall be protected from moisture traps. A con-

formal coating material or solder mask applied prior to

component assembly shall be used for such protection.

Coating(s) shall be sufficient to insure electrical integrity.

This requirement is applicable to components with or with-

out insulating sleeving.

4.1.7 Clearances The minimum clearance between

component leads or components with metal cases and any

other conductive path shall be determined by their electri-

cal parameters and mechanical considerations.

4.1.8 Physical Support Components should be mounted

in such a manner as to meet the physical requirements of

the device. The mounting techniques must give results

which are consistent with the respective physical environ-

ment which the device must be able to withstand. Consid-

erations should include mechanical shock, mechanical

vibration, thermal shock, constant acceleration (centrifuge),

and storage temperatures.

4.1.9 Height Restriction Height restriction for general

component mounting, normally pertains to axial-leaded

components mounted vertically, or to large parts that have

a speciﬁc height geometry. In general, the proﬁle of com-

ponents should be kept as low as possible to the surface of

the substrate. A maximum allowable vertical height from

the mounting surface should be 15 mm [0.60 inches].

4.1.10 Heat Dissipation Heat generated during circuit

operation shall be controlled by the use of heat sinking

devices of a size and conﬁguration adequate to dissipate

the heat to the extent that the maximum allowable operat-

ing temperature of the hybrid circuit is not exceeded.

This may include the use of a clamp, thermal ground plane

(including copper foil), separately manufactured heat sink-

ing elements, or thermally conductive adhesive. Any heat

dissipation technique or device shall permit appropriate

cleaning to remove contaminants from the assembly. Con-

ductive materials used to transfer heat between parts and

heat sink shall be compatible with assembly and cleaning

processes.

4.1.11 Stress Relief The leads of components mounted

horizontally with their bodies in direct contact with the

printed board shall be mounted with a method that ensures

that stress relief is not reduced or negated by solder ﬁll in

the lead bends.

4.1.12 Automatic Assembly When automatic compo-

nent insertion and attachment is employed, there are sev-

eral hybrid circuit design parameters that must be taken

into account that are not applicable when manual assembly

techniques are used; these are shown in the following para-

graphs.-

IPC-859-4-1

Figure 4–1 Example of orientation marks on chip

carriers.

PIN 1

CORNER MARK

(Typ. & Pl.)

December 1989 IPC-D-859