IPC-D-859.pdf - 第70页
A. Part number and revision letter B. Part traceability or lot number 6.5.4 Number of Layers The number of layers of each coupon shall be the same as the number of layers in the associated end-product hybrid circuit. 6.5…
be prepared as a part of the drawing package. This final bill
may be a computer listing, or may be in drawing format.
6.0 Quality Assurance This section provides require-
ments and considerations for the quality and quality assur-
ance provisions that incorporate test coupons into the board
design. This section also includes a brief discussion of
bare-board testing.
6.1 General Quality concepts should be included in all
aspects of the hybrid circuit design. Quality considerations
apply to manufacture, assembly and bare board assembly
testing. The design concepts are the key to the capability of
achieving quality in the previously mentioned areas. Good
workmanship insures that quality. In lieu of test coupons,
production boards may be employed in tests used to deter-
mine the acceptability of hybrid circuits.
6.2 Bare Board Testing Bare board testing is an electri-
cal evaluation of the completely fabricated end-product cir-
cuit without components. Electrical checks are made for
point-to-point continuity, low resistance (opens), and high
resistance (shorts).
Visual surface characteristics may be verified using auto-
matic optical inspection.
6.2.1 Approaches There are two approaches to bare
board testing, namely:
A. Test all lands.
B. Test for opens at low-voltage levels, and test for shorts
at high-voltage levels.
6.3 Design Considerations
6.3.1 Lands On Grid
All lands to be involved in bare
board testing shall be on grid, so that universal test fixtures
can be used. (Commonly used grids are 2.54 mm [0.100
inch] and 1.27 mm [0.050 inch].)
6.3.2 Lands Off Grid If the conditions in 6.4.2.1 are not
possible, the board layout should attempt to limit the
required number of off-grid lands, so that test fixtures with
flexible pins may be used, or so that a dedicated test fix-
ture can be made cost-effectively.
6.3.3 Power-to-Ground Measurement Information
should be on the initial design documentation that indicates
lands for measuring power-to-ground relationships.
6.4 Test Tapes Test tapes should be generated from
known, good circuits.
6.5 Test Circuitry Quality conformance testing may be
done on the finished part, or quality conformance test cir-
cuitry, or a combination of both.
The coupons should be produced on separate substrates;
however, all coupons required shall be shown on the mas-
ter drawing artwork and the production master. Figure 6–1
shows the individual coupon layout for layer 1, and Figure
6–7 depicts artwork configuration for layers 1 through 10.
Dimensions shown in Figures 6–2 through 6–6 apply to all
layers.
Special test coupons F through L are shown in Figures 6–8
through 6–13. These may be used for additional testing as
indicated, at the designer’s discretion; however, when their
use is specified, they shall also be shown on the master
drawing artwork and the production master.
6.5.1 Quantity At least one complete set of quality con-
formance test circuitry (coupons A through E) shall be pro-
vided with each lot of each part number produced.
6.5.2 Manufacturing Requirements The coupons shall
be fired under normal furnace loading conditions. They
shall be processed utilizing the same production equip-
ment, procedures, and personnel used in regular produc-
tion. Operations shall be divided up betweeen identical or
similar types of equipment, operating shifts, and personnel;
and all coupons shall be totally representative of the prod-
uct.
6.5.3 Identification The coupons are to be identified
with the following:
IPC-859-5-43
Figure 5–43 Routing conductors through multiple
dielectric layers
▼
▼
▼
▼
▼
▼
▼
▼
▼
VIA
VIA
SUBSTRATE
VIA
TOP LEVEL
SECOND LEVEL
NOT PREFERRED
VIAS NOT STAGGERED
PREFERRED DESIGN-
VIAS ARE STAGGERED
BOTTOM LEVEL
IPC-859-5-44
Figure 5–44 Use of a blind through-hole land
Substrate
Top Conductor Blind Land on
Second Level
Bottom
Conductor
▼
▼
▼
December 1989 IPC-D-859
63
A. Part number and revision letter
B. Part traceability or lot number
6.5.4 Number of Layers The number of layers of each
coupon shall be the same as the number of layers in the
associated end-product hybrid circuit.
6.5.5 Test Coupon Examples For Quality Conformance
Testing
6.5.5.1 Coupon A
This coupon (Figure 6–2) is used to
evaluate bondability, weldability, solderability, and shorts.
6.5.5.2 Coupon B This coupon (Figure 6–3) is used to
evaluate adhesion, passivation, dielectric resistance, and
outgassing.
6.5.5.3 Coupon C This coupon (Figure 6–4) is used to
evaluate circuit continuity, temperature cycling, thermal
cycling, and construction integrity.
6.5.5.4 Coupon D This coupon (Figure 6–5) is used to
evaluate dielectric withstanding voltage and outgassing.
6.5.5.5 Coupon E This coupon (Figure 6–6) is used to
evaluate insulation resistance. Figure 6–7 shows individual
layer artwork configuration for up to a 10-layer board.
Additional layers may be added as required.
6.5.5.6 Coupon F This coupon (Figure 6–8) is used to
evaluate resistance to electromigration. While it is designed
primarily for tests on surface layers, it may be adapted for
modified inner layer testing by the addition of vias to the
access lands at each end of the pattern.
Conductor lines are 0.10 mm [0.004 in.] with a 0.15 mm
[0.006 in.] line spacing. Test conditions, 20VDC, for 20
minutes under a drop of DI water.
6.5.5.7 Coupon G This coupon (Figure 6–9) is used to
IPC-859-6-1
Figure 6–1 Layer 1—Individual coupon layout
IPC-D-859 December 1989
64
evaluate via resistivity. Vias are on 1.0 mm [0.040 in.] cen-
ters with interconnecting conductors 0.10 mm [0.004 in.]
wide. Via size should be typical of that used on the parts in
the lot.
6.5.5.8 Coupon H This coupon (Figure 6–10) is used to
evaluate capacitance and current density. Pattern is 10
square millimeters [0.0015 square inches].
6.5.5.9 Coupon J This coupon (Figure 6–11) is used to
measure conductor resistivity on a dielectric. Pattern is 200
squares long, printed on two layers of dielectric.
6.5.5.10 Coupon K This coupon (Figure 6–12) is used to
evaluate conductor resistivity on a substrate. Pattern is
same as Coupon J, except it is printed directly on the sub-
strate.
6.5.5.11 Coupon L This coupon (Figure 6–13) is used to
evaluate fine line resistivity. Pattern is 200 squares long,
printed on dielectric.
Figures 6–14 through 6–17 show test circuit configuration
for top and bottom layers, insulation layer, and via fill
layer.
6.5.6 Added Test Circuitry When additional testing is
desired for via tests, capacitance testing, or conductor resis-
tivity, the artwork shown in Figures 6–18 through 6–20
may be used. These need not be included in the master
drawing artwork.
IPC-859-6-2
Figure 6–2 Test Coupon A (Layer 2)
W
16 mm [0.630 in]
L
Land size:
2.0 x 2.0 mm [0.079 in x 0.079 in]
square (Typ.)
L = ( )= 2.5 mm [0.098 in]
Nr = No. of layers (Even Nos.)
= No. of layers + 1 (Odd Nos.)
Nr 3.5 mm
2 [0.138in]
x
December 1989 IPC-D-859
65