IPC-D-859.pdf - 第66页

5.5.4 Pinholes There shall be no pinholes on the 1:1 art- work master lar ger than 25 µm [0.001 inch], or which reduce the artwork conductor width by more than 10 per- cent. Areas outside of the functional board outline …

Magnetic tape may also be supplied for drilling and rout-

ing machines. Data tapes supplied in the D–350 series for-

mat, shall be single- image, unless otherwise speciﬁed.

5.5.1 Artwork Masters A copy of the 1:1 artwork mas-

ter for each layer shall be provided as part of the drawing

set. Each artwork master shall contain a minimum of three

(3) dimensioned targets. These targets shall be on grid, and

shall register with each other from layer to layer.

5.5.2 Base Material The artwork master shall be sup-

plied on 200 µm [0.0075 ± 0.005 inch] thick biaxially ori-

ented, dimensionally stable, polyester type ﬁlm, or on glass

photographic plates.

5.5.3 Accuracy The accuracy of the artwork master shall

be such that each artwork master shall have all centers of

land areas, conductors, and other features located with

respect to the true grid position within the positional toler-

ances established. For the composite artwork master, the

features of all layers shall coincide within the tolerance

speciﬁed.

IPC-859-5-38

Figure 5–38 Worksheet for determining resistor pastes based on number of squares needed.

December 1989 IPC-D-859

5.5.4 Pinholes There shall be no pinholes on the 1:1 art-

work master larger than 25 µm [0.001 inch], or which

reduce the artwork conductor width by more than 10 per-

cent. Areas outside of the functional board outline shall not

be subject to inspection, and may have pinholes. Pinholes

within the functional board outline that are covered with

opaque ink shall be acceptable.

5.5.5 Opaque Defects (Specks) There shall be no

opaque defects within the functional board outline larger

than 25 µm [0.001 inch] on the 1:1 artwork master, or

which reduce the conductor width by more than 10 percent.

Areas outside of the functional board outline shall not be

subject to inspection, and may have opaque defects. Areas

where opaque defects within the functional board outline,

that have been removed with a sharp pointed hand tool,

shall be acceptable.

5.5.6 Reproduction Conditions The temperature, rela-

tive humidity, date, and photographic facility identiﬁcation

shall appear on each artwork master ﬁlm in such a manner

that the artwork master can be readily separated from any

photographic reproductions. Alternately, traceability to

records from automatic monitoring and recording facilities

can be speciﬁed.

5.5.7 Packaging and Handling of Artwork Masters

Each artwork master 360 mm x 450 mm [14 x 17 inches]

or under, shall be separately packaged in a glass lined or

polyethylene envelope. Artwork master 360 mm x 450 mm

[14 x 17 inches] to 450 mm x 560 mm [14 x 17 inches]

shall be packaged ﬂat in a box, and constrained with a

sheet of low density foam. Artwork master larger than 450

mm x 560 mm [14 x 17 inches] may be rolled (minimum

diameter 76 mm [3 inches]) and enclosed in a container

made of ﬁberboard or metal. One inch rubberized hair felt

or equivalent shall be placed in each end of the container

for protection.

5.6 Documentation The documentation package for a

printed wiring board should include the master drawing

and copies of the secondary artwork masters. More than

one copy of the master drawing should be supplied to the

vendor. Other documentation, which may be included with

package, could include mag tapes for the generation of

photoplotted artwork and NC tapes for component place-

ment. Documentation shall meet the requirements of IPC-

D-325.

Numerical control tapes should be included with the ven-

dor documentation package when available. These can be

in a paper tape format, or on mag tape, depending on the

vendor’s capabilities. The code in which the tapes are writ-

ten should also be provided.

5.6.1 Master Drawing The master drawing shall meet

the requirements of paragraph 3.3 and IPC-D-325 and

include, as a minimum, the information detailed in Table

5–5.

5.6.1.2 Marking The master drawing shall include the

speciﬁcation requirement for all supplemental marking,

that is, those markings other than those etched in the pat-

tern. The drawing note shall include the kind of ink or

IPC-859-5-39

Dim

Min/

Max

Producibility mm

[inch]

Most ↔ Least

ABC

Screened resistor

size:

• Number of

squares

L/W

Min

Max

0.5 sq.

5.0 sq.

0.5 sq.

10.0 sq.

0.3 sq.

10.0 sq.

• Length L Min 1.27

[0.050]

1.02

[0.040]

1.02

[0.040]

• Width, ±1% tol-

erance

W Min 1.02

[0.040]

0.89

[0.035]

0.89

[0.035]

• Width, 5% toler-

ance

W Min 0.76

[0.030]

0.64

[0.025]

0.64

[0.025]

Conductor termi-

nal, distance

beyond width

of resistor

Min 0.38

[0.015]

0.25

[0.010]

0.20

[0.008]

Conductor termi-

nal, distance

beyond length

of resistor

Min 0.38

[0.015]

0.25

[0.010]

0.20

[0.008]

Resistor overlap,

onto conductor

terminal

Min 0.25

[0.010]

0.20

[0.008]

0.20

[0.008]

Conductors,

distance from

resistor

Min 0.51

[0.020]

0.38

[0.015]

0.38

[0.015]

Edge of sub-

strate, distance

from resistor

Min 0.76

[0.030]

0.51

[0.020]

0.51

[0.020]

Figure 5–39 Thick-ﬁlm screened resistor sizes

and locations

▼

Screened

Resistor

IPC-D-859 December 1989

paint, the color, and the side(s) of the board to be marked.

If the marking is to be made by silk screen or similar

method, a layout of the marking shall be included as the

last sheet(s) of the artwork master, and shall be referenced

in the marking note.

5.6.1.3 Traceability Marking The master drawing shall

speciﬁcally indicate the location for the manufacturer’s

code and all other required traceability markings on the

board. The part number change letter and its location, shall

be indicated on the drawing.

A drawing note shall indicate the acceptable methods of

marking (ink, rubber, stamp, electric pencil, etching, etc.)

and color if applicable.

5.6.2 Assembly Drawing The hybrid circuit assembly

drawing shall cover circuitry on which separately manufac-

tured parts have been added. The hybrid circuit assembly

drawing shall be compatible with IPC-D-325, and may

include at least the following:

a. Parts and material list.

b.Component mounting and installation requirements.

c. Cleanliness requirements.

d.Location and identiﬁcation of materials.

e. Location and identiﬁcation of all components.

f. Component orientation and polarity.

g.Applicable ordering data.

h.Structural details when require for support and rigidity.

Table 5–5 Master Drawing Detail Descriptions

A Hybrid Circuit Details 1. The type, size and shape of the hybrid circuit and all tolerance conditions thereof

2. Dielectric separation between layers

3. Bow and twist allowances

4. Overall thickness requirements including tolerances

B Materials 1. Type class and grade of material, including color if appropriate

2. Plating and coating material(s) type and thickness(es)

3. Marking inks or paint and permanency

C Via Details 1. The size, location and tolerances for all vias

D Conductor Deﬁnition 1. Shape and arrangement of both conductor and non-conductor patterns on each layer

of the hybrid circuit (copies of the production master(s) or copies of artwork may be

used to deﬁne these patterns)

2. Separate views of each conductor layer

3. Dimensions either speciﬁcally or by reference to a grid system, for any and all

pattern features not controlled by hole size and location

4. Minimum conductor width and spacing on the ﬁnished hybrid circuit

5. Dimensions for critical pattern features which may affect circuit performance because

of distributive inductance or capacitance effects

6. Conductor layer identiﬁcation

E Marking 1. Hybrid circuit identiﬁcation marking

2. Size, shape and location of reference designation and legend marking, if required.

3. Serialization and revision level marking

F Processing Conditions 1. Processing allowances that were used in the design of the hybrid circuit, including

but not limited to:

a. Conductor width allowance

b. Conductor spacing allowance

c. Land fabrication allowance

d. Solder mask or cover layer registration allowance

2. Applicable processing speciﬁcations

3. Location of quality conformance coupon or circuitry

G Design Concepts 1. Maximum rated voltage (maximum voltage between two non-connected adjacent

conductors with the greatest potential difference

2. Identiﬁcation of testing and test point location

3. Modular grid system(s) used to identify all holes, test points, lands and overall

dimensions

a. Metric grid—2.0, 1.0, 0.5 or multiples of 0.1 mm

b Inch based grid—0.100, 0.050, 0.025 or multiples of 0.005 inches

(see Section H-3 of this table)

H Documentation Practices 1. All terms used on the master drawing shall conform to this standard and IPC-T-50

2. Notes either included on the ﬁrst sheet(s) or location of notes speciﬁed on the ﬁrst

sheet(s)

3. Indication of grid using X-Y control dimensions or grid scales. Grids should not be

reproduced on the master drawing to maintain clarity of conductor patterns

December 1989 IPC-D-859