IPC-D-859.pdf - 第41页
4.4 Component Lead Sockets 4.4.1 Integrated Circuit Sockets 4.4.1.1 DIP Sockets Sockets, such as that shown in Fig- ure 4–16 are designed for low-cost, high-density , mounting of DIP components. They are generally design…
IPC-859-4-4
Figure 4–4 SO 16 integrated circuit package
IPC-859-4-5
Figure 4–5 SOT-89 package drawing example
IPC-D-859 December 1989
34
4.4 Component Lead Sockets
4.4.1 Integrated Circuit Sockets
4.4.1.1 DIP Sockets
Sockets, such as that shown in Fig-
ure 4–16 are designed for low-cost, high-density, mounting
of DIP components. They are generally designed to resist
solder wicking into the socket or cavity, and have provi-
sions that provide the needed clearance of the socket above
the substrate.
4.4.1.2 Chip Carrier Socket Sockets such as that shown
in Figure 4–17 can be used with most of the chip carriers
described in 4.3.1. They can be either surface mounted or
through-hole mounted, depending on the termination con-
figuration of the socket contacts.
When they are surface mounted, they can also be obtained
with a mechanical contact pressure interface to the printed
board. The advantages of this type of socket are the ease of
replacement of the socket, and the absence of damage due
to soldering and unsoldering. A disadvantage is that a sec-
ond mechanical interface is now in the circuit path.
4.5 Connectors and Interconnects One of the critical
design requirements for multilayer hybrid circuits is to pro-
vide a method of interconnection for signal and power
input/outputs.
This is normally done by surface contact to lands on the
outer layer(s), typically with a conductive header or by the
use of flexible circuitry.
When the header is used, it may be soldered, welded or
brazed to the surface lands, with its contacts projecting
beyond the periphery of the substrate. In selecting material
for the header, consideration should be given to such items
IPC-859-4-6
Figure 4–6 Plastic-leaded chip carrier lead misalignment
IPC-859-4-7
Figure 4–7 Round or coined lead
December 1989 IPC-D-859
35
as mismatch of Coefficients of Thermal Expansion,
solderability/weldability of the material, and protection of
its contacts from corrosion during storage.
When flexible cable is used, it may be soldered directly to
land patterns on the substrate. Proper mechanical support,
using tie-down bars, or adhesives, shall be used to prevent
stresses on the solder joints.
IPC-859-4-8
Figure 4–8 JEDEC 1.27 mm [0.050 inch] chip carrier packages
IPC-859-4-9
Figure 4–9 Common features of JEDEC 1.27 mm [0.050 inch] center chip carriers.
IPC-D-859 December 1989
36