IPC-D-859.pdf - 第54页

T able 5–1 Chip Mounting Lands Land Size and Spacing Minimum Dimension mm [inch] Nominal Dimension mm [inch] Maximum Dimension mm [inch] Figure 5–16 Item Semiconductor chip-to-chip spacing (1) (1) None 1 Semiconductor ch…

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5.3.2.6 Land Pattern for Leadless Chip Carriers The
attachment lands for surface mounting leadless chip carri-
ers should be the same width as the component terminal
(castiliation maximum) plus 0.13 mm [0.005 inch] when-
ever possible. The land length should extend between 0.4
to 1.0 mm [0.016 inch to 0.04 inch] beyond the maximum
chip carrier outline on all foursides to create a horizontal
solder fillet length equal to the vertical fillet rise (see Fig-
ure 5–21). The design of fan-out to interconnect the basic
land pattern to other circuitry/devices is dependent on wir-
ing density, testability, assembly, repairability, and routabil-
ity requirements. Figure 5–22 shows some examples of
possible fan-out patterns for leadless chip carriers. Chip
carrier land sites should be located on a fixed grid within
the hybrid circuit to optimize testing. This grid should be
compatible with assembly and testing equipment, so as to
minimize the amount of specialized and complex equip-
ment necessary.
5.3.2.7 Lands for Leaded Chip Carriers The land size
for ceramic and for leaded chip carriers should match the
lead configurations. J shaped leads should have the land
width be equal to or 0.12 mm [0.005 inch] larger than the
width of the lead. The length should extend between 0.4 to
1.0 mm [0.016 inch to 0.040 inch] beyond both sides of the
foot of the J pattern. Other types of leads used for chip
carriers should have the land commensurate with the lead
configuration, in order to create a horizontal solder fillet
length at the toe and heel of the lead configuration, as
shown on Figure 5–23.
5.3.2.8 Lands for Ribbon Leaded Surface Mounted
Parts
The land requirements for mounting ribbon leaded
parts, such as ‘‘flat packs’’, ‘‘quad packs’’, or small outline
devices, shall preferably be rectangular. The minimum land
width shall be equal to or exceed the maximum lead width,
providing room for both solder fillets at both the heel and
toe of the ribbon lead. The minimum land width shall be
approximately one and one-half times the width of the lead,
or 0.12 mm [0.005 inch], whichever is less (see Figure
5–24). Flat pack termination shall be staggered to permit
greater spacing wherever possible. The center position of
ribbon leaded components should be on a fixed grid, wher-
ever possible, to facilitate testing.
5.3.2.9 Lands for Flattened Round Leads Flattened
IPC-859-5-14
Obstacle Height
H mm [inch]
Wire Bond-to-Obstacle
Minimum Spacing
W mm [inch]
0.25 [0.020] 1.02 [0.040]
1.02 [0.040] 1.14 [0.045]
1.52 [0.060] 1.27 [0.050]
2.03 [0.080] 1.40 [0.055]
Over 2.54 [0.100] 1.15 [0.065]
Figure 5–14 Locating wire bond lands and sizing
components so as to provide access/clearance for
bonding tool head.
Obstacle
Obstacle
W
W
H
H
▼
▼
▼
▼ ▼
▼
▼
▼
▼
▼
IPC-859-5-15
Dim
Producibility mm [inch]
Most ↔ Least
ABC
Discrete leaded component:
• Metallized land overlap,
for epoxy or solder
attachment.
A 0.38
[0.015]
0.25
[0.010]
0.25
[0.010]
• Distance from leaded
component
F 1.02
[0.040]
1.02
[0.040]
1.02
[0.040]
Semiconductor chip:
• Die bond land overlap,
for eutectic or epoxy
attachment.
B 0.38
[0.015]
0.25
[0.010]
0.25
[0.010]
• Land distance from
other metallization
E 0.51
[0.020]
0.38
[0.015]
0.38
[0.015]
Leadless component (chip
capacitor or chip resistor):
• Ceramic body overlap
onto land
C 0.38
[0.015]
0.25
[0.010]
0.25
[0.010]
• Metallized end land
overlap onto land, for
epoxy or solder
D 0.51
[0.020]
0.38
[0.015]
0.38
[0.015]
• Distance from leaded
component
F 1.02
[0.040]
1.02
[0.040]
1.02
[0.040]
Figure 5–15 Minimum lands for component mounting
Leadless
Component
(Chip Capacitor
or Resistor)
▼
Semicon-
ductor
Chip
Discrete
Leaded
Component
▼
▼
▼
▼
▼
▼
▼
▼
▼
▼
▼
▼
▼
▼
▼
▼
▼
▼
▼
▼
▼
E
B
B
E
F
D
C
C
A
A
A
December 1989 IPC-D-859
47
Table 5–1 Chip Mounting Lands
Land Size and Spacing
Minimum
Dimension
mm [inch]
Nominal
Dimension
mm [inch]
Maximum
Dimension
mm [inch]
Figure 5–16
Item
Semiconductor chip-to-chip spacing (1) (1) None
1
Semiconductor chip mounting land (width and length
beyond chip)
0.25 [0.010] 0.32 [0.0125] None
2
Passive chip-to-bonding land wiring distance beyond chip
(width or length)
0.76 [0.030] 0.82 [0.0325] 0.100
3
Passive chip mounting land (beyond chip width) 0.13 [0.005] 0.19 [0.0075] None
4
Passive chip mounting land (beyond chip end) 0.38 [0.015] 0.43 [0.017] None
5
Passive chip-to-conductor overlap 0.25 [0.010] 0.32 [0.0125] None
6
Passive chip-to-wire bonding land spacing 1.02 [0.040] 1.27 [0.050] None
7
Inductor lead mounting land (width and length) 1.02 [0.040] 1.27 [0.050] None
8
Inductor body-to-wire bonding land 0.13 [0.005] 0.19 [0.0075] None
10
Passive chip end-to-end spacing 1.02 [0.040] 1.21 [0.050] None
9
(1) Use 0.81 [0.032 inch] spacing between chips.
IPC-859-5-16
Figure 5–16 Nominal dimensions for chip mounting lands (see Table 5–1)
R
C
L
CR
CR
9
6
3
5
4
7
10
1
2
8
1.27 [0.050]
1.52 [0.060]
0.32 [0.0125]
0.32 [0.0125]
0.8 [0.032]
Minimum
1.27 [0.050]
This distance
dependent on
chip width
This distance
dependent on
chip width
0.19
[0.0075]
1.27 [0.050]
0.32 [0.0125]
0.19 [0.0075]
0.44 [0.0175]
Dimensions
in mm 0.82 [0.0325]
IPC-D-859 December 1989
48
round leads shall have a land which will provide the seat-
ing so that the heel and the terminal relationship is in
accordance with Figure 5–25. Leads shall be seated with no
side overhang. Toe overhang is acceptable, provided that
the flattened lead in contact with the terminal area is a
minimum of 150% of the unflattened lead diameter, and the
overhang does not reduce the spacing to adjacent parts to
less than that specified on the assembly drawing.
5.3.2.10 Lead Frame Bonding Lands Figure 5–26 estab-
lished minimum values for size and location of lead frame
bonding lands.
5.3.3 Wire Bonds Wire-bond connection should never be
made between lands on IC chips. A method for making
such connections is illustrated in Figure 5–27
Wires should never cross other wires or chip components.
When wire bonds cross electrically uncommon conductor
IPC-859-5-17
Figure 5–17 Exit land/alignment/misalignment
considerations for hybrid packages
IPC-859-5-18
Figure 5–18 Examples of lead/pin identification assignments
19 X 19 [0.75" X 0.75"] SUBSTRATE
OUTLINE FOR 16 LEAD
25 X 25 [1" X !"] HAC PAC
PACKAGE
8.76 X 11.2 [0.345 X 0.445]
SUBSTRATE
OUTLINE FOR
10 PIN
12.7 X 12.7 [0.5 X 0.5]
PLATFORM
PACKAGE
8.4 X 8.4 [0.33 X 0.33]
SUBSTRATE
OUTLINE FOR 
15.24 [0.0600]
DIA. TO 20.32 [0.800]
PACKAGE
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
10 9 8 7 6 9 8 7
1 2 3 4 5
10
11
12
6
5
4
1 2 3
DIMENSIONS IN mm [INCHES]
IPC-859-5-19
Figure 5–19 Probe land positioning to assist resistor
trimming.
December 1989 IPC-D-859
49