CMV12000_DS000603_6-00.pdf - 第11页

Document Feedback CMV12000 Pin Assignment Datasheet • PUBLIC DS000603 • v6 - 00 • 2023 -Sep- 22 84 │ 10 Number Name Type Description E12 OUT42_P LVDS output LVDS positive output channel 42 E13 OUT46_N LVDS output LVDS ne…

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CMV12000

Pin Assignment

Datasheet • PUBLIC

DS000603 • v6-00 • 2023-Sep-22

84 │ 9

Number

Name

Type

Description

GND

Ground

Ground pin

VDD33

Supply

3.3 V supply

VCLAMP

Bias

Decouple with 100 nF to GND

VRES_L

Bias

Reset low voltage (decouple with 100 nF to GND)

VTF_LOW1

Bias

Transfer low voltage 1 (connect to GND)

OUT3_N

LVDS output

LVDS negative output channel 3

OUT3_P

LVDS output

LVDS positive output channel 3

OUT6_N

LVDS output

LVDS negative output channel 6

D10

OUT6_P

LVDS output

LVDS positive output channel 6

D11

OUT10_N

LVDS output

LVDS negative output channel 10

D12

OUT10_P

LVDS output

LVDS positive output channel 10

D13

OUT15_N

LVDS output

LVDS negative output channel 15

D14

OUT15_P

LVDS output

LVDS positive output channel 15

D15

OUT17_N

LVDS output

LVDS negative output channel 17

D16

OUT17_P

LVDS output

LVDS positive output channel 17

D17

OUT20_N

LVDS output

LVDS negative output channel 20

D18

OUT20_P

LVDS output

LVDS positive output channel 20

D19

OUT24_N

LVDS output

LVDS negative output channel 24

D20

OUT24_P

LVDS output

LVDS positive output channel 24

D21

OUT27_N

LVDS output

LVDS negative output channel 27

D22

OUT27_P

LVDS output

LVDS positive output channel 27

D23

OUT30_N

LVDS output

LVDS negative output channel 30

D24

OUT30_P

LVDS output

LVDS positive output channel 30

D25

GND

Ground

Ground pin

D26

VDD33

Supply

3.3 V supply

D27

GND

Ground

Ground pin

D28

VDD_PIX

Supply

3.0 V supply

D29

GND

Ground

Ground pin

D30

VDD_PIX

Supply

3.0 V supply

VDD18_PLL

Supply

PLL 1.98 V supply (unused)

VDD_RES

Supply

3.3 V supply

GND

Ground

Ground pin

DIO2

Ground

Connect to ground

LVDS_CLK_N

LVDS input

LVDS input clock N

LVDS_CLK_P

LVDS input

LVDS input clock P

OUT35_N

LVDS output

LVDS negative output channel 35

OUT35_P

LVDS output

LVDS positive output channel 35

OUT38_N

LVDS output

LVDS negative output channel 38

E10

OUT38_P

LVDS output

LVDS positive output channel 38

E11

OUT42_N

LVDS output

LVDS negative output channel 42

Document Feedback

CMV12000

Pin Assignment

Datasheet • PUBLIC

DS000603 • v6-00 • 2023-Sep-22

84 │ 10

Number

Name

Type

Description

E12

OUT42_P

LVDS output

LVDS positive output channel 42

E13

OUT46_N

LVDS output

LVDS negative output channel 46

E14

OUT46_P

LVDS output

LVDS positive output channel 46

E15

GND

Ground

Ground pin

E16

GND

Ground

Ground pin

E17

OUT51_N

LVDS output

LVDS negative output channel 51

E18

OUT51_P

LVDS output

LVDS positive output channel 51

E19

OUT55_N

LVDS output

LVDS negative output channel 55

E20

OUT55_P

LVDS output

LVDS positive output channel 55

E21

OUT59_N

LVDS output

LVDS negative output channel 59

E22

OUT59_P

LVDS output

LVDS positive output channel 59

E23

OUT62_N

LVDS output

LVDS negative output channel 62

E24

OUT62_P

LVDS output

LVDS positive output channel 62

E25

GND

Ground

Ground pin

E26

VDD33

Supply

3.3 V supply

E27

GND

Ground

Ground pin

E28

SPI_IN

Digital input

SPI data input pin

E29

T_EXP2

Digital input

Input pin for external exposure

E30

CLK_IN

Digital input

Master input clock

CMDN

Bias

Decouple with 100 nF to GND

CMDP

Bias

Decouple with 100 nF to VDD33

CMDP_COMP18

Bias

Decouple with 100 nF to VDD33

DIO1

Ground

Connect to ground

VDD33

Supply

3.3 V supply

OUT33_N

LVDS output

LVDS negative output channel 33

OUT33_P

LVDS output

LVDS positive output channel 33

OUT37_N

LVDS output

LVDS negative output channel 37

OUT37_P

LVDS output

LVDS positive output channel 37

F10

OUT40_N

LVDS output

LVDS negative output channel 40

F11

OUT40_P

LVDS output

LVDS positive output channel 40

F12

OUT44_N

LVDS output

LVDS negative output channel 44

F13

OUT44_P

LVDS output

LVDS positive output channel 44

F14

OUT48_N

LVDS output

LVDS negative output channel 48

F15

OUT48_P

LVDS output

LVDS positive output channel 48

F16

OUT49_N

LVDS output

LVDS negative output channel 49

F17

OUT49_P

LVDS output

LVDS positive output channel 49

F18

OUT53_N

LVDS output

LVDS negative output channel 53

F19

OUT53_P

LVDS output

LVDS positive output channel 53

F20

OUT57_N

LVDS output

LVDS negative output channel 57

F21

OUT57_P

LVDS output

LVDS positive output channel 57

Document Feedback

CMV12000

Pin Assignment

Datasheet • PUBLIC

DS000603 • v6-00 • 2023-Sep-22

84 │ 11

Number

Name

Type

Description

F22

OUT60_N

LVDS output

LVDS negative output channel 60

F23

OUT60_P

LVDS output

LVDS positive output channel 60

F24

Not connected

F25

Not connected

F26

VDD33

Supply

3.3 V supply

F27

GND

Ground

Ground pin

F28

SPI_EN

Digital input

SPI enable input pin

F29

VRAMP2

Bias

Start voltage second ramp (decouple with 100 nF to GND)

F30

SYS_RES_N

Digital input

Input pin for sequencer reset

VDD_PIX

Supply

3.0 V supply

CMDN_OSC

Bias

Decouple with 100 nF to GND

DIO4

Ground

Connect to ground

VDD_RES

Supply

3.3 V supply

GND

Ground

Ground pin

OUTCLK_N

LVDS output

LVDS negative clock output signal

OUTCLK_P

LVDS output

LVDS positive clock output signal

OUT36_N

LVDS output

LVDS negative output channel 36

OUT36_P

LVDS output

LVDS positive output channel 36

G10

OUT39_N

LVDS output

LVDS negative output channel 39

G11

OUT39_P

LVDS output

LVDS positive output channel 39

G12

OUT43_N

LVDS output

LVDS negative output channel 43

G13

OUT43_P

LVDS output

LVDS positive output channel 43

G14

OUT47_N

LVDS output

LVDS negative output channel 47

G15

OUT47_P

LVDS output

LVDS positive output channel 47

G16

OUT50_N

LVDS output

LVDS negative output channel 50

G17

OUT50_P

LVDS output

LVDS positive output channel 50

G18

OUT54_N

LVDS output

LVDS negative output channel 54

G19

OUT54_P

LVDS output

LVDS positive output channel 54

G20

OUT58_N

LVDS output

LVDS negative output channel 58

G21

OUT58_P

LVDS output

LVDS positive output channel 58

G22

OUT61_N

LVDS output

LVDS negative output channel 61

G23

OUT61_P

LVDS output

LVDS positive output channel 61

G24

OUT64_N

LVDS output

LVDS negative output channel 64

G25

OUT64_P

LVDS output

LVDS positive output channel 64

G26

TDIG2

Digital output

Test pin for digital sequencer signals (do not connect)

G27

TDIG1

Digital output

Test pin for digital sequencer signals (do not connect)

G28

SPI_OUT

Digital output

SPI data output pin

G29

VRAMP1

Bias

Start voltage first ramp (decouple with 100 nF to GND)

G30

FRAME_REQ

Digital input

Frame request pin

GND

Ground

Ground pin