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Document Feedback CMV12000 Functional Description Datasheet • PUBLIC DS000603 • v6 - 00 • 2023 -Sep- 22 84 │ 20 ● 64 Data channels ● 1 Control channel ● 1 Clock channel The 64 data channels are u sed to transfer 8-bit, 1…
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CMV12000
Functional Description
Datasheet • PUBLIC
DS000603 • v6-00 • 2023-Sep-22
84 │ 19
7 Functional Description
7.1 Sensor Architecture
Figure 2 shows the image sensor architecture. The internal sequencer generates the necessary
signals for image acquisition. The image is stored in the pixel (global shutter) and they are read out
sequentially, row-by-row. On the pixel output, an analog gain is possible. The pixel values then passes
to a column ADC cell, in which ADC conversion is performed. The digital signals are then read out
over multiple LVDS channels. Each LVDS channel reads out 128 adjacent columns of the array. The
read-out of the pixel array is performed on both sides (top and bottom) of the pixel array to speed up
the read-out process and achieve the frame rate of 300 fps at full resolution and 10-bit. In each line
read-out cycle, two lines are selected for read-out. In the Y-direction, rows of interest are selected
through a row-decoder, which allows a flexible windowing. Control registers are foreseen for the
programming of the sensor. These register parameters are uploaded via a four-wire SPI interface. A
temperature sensor, which can be read out over the SPI interface, is also included.
7.1.1 Pixel Array
The pixel array consists of 4096 x 3072 square global shutter pixels with a pitch of 5.5 μm (5.5 μm x
5.5 μm). This results in an optical area of 22.5 mm x 16.9 mm (28.1 mm diameter).
The pixels are designed to achieve maximum sensitivity with low noise (using CDS) and low PLS
specifications. Micro lenses are placed on top of the pixels for improved fill factor and quantum
efficiency.
There are 16 dark reference columns available on the sensor (columns 0 to 7 and 4088 to 4095)
which can be enabled/disabled by programming the appropriate sensor register.
7.1.2 Analog Front End
The analog front end consists of two major parts, a column amplifier block and a column ADC block.
The column amplifier prepares the pixel signal for the column ADC and applies analog gain if desired
(programmable using the SPI interface). The column ADC converts the analog pixel value to an 8-, 10-
or 12-bit value and can apply a gain. A digital offset can also be applied to the output of the column
ADCs. All gain and offset settings can be programmed using the SPI interface.
7.1.3 LVDS Block
The LVDS block converts the digital data coming from the column ADC into standard serial LVDS data
running at maximum 600 Mbit/s. The sensor has 66 LVDS output pairs:
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● 64 Data channels
● 1 Control channel
● 1 Clock channel
The 64 data channels are used to transfer 8-bit, 10-bit or 12-bit data words from sensor to receiver.
The output clock channel transports a DDR clock (max 300 MHz), synchronous to the data on the
other LVDS channels. This clock can be used at the receiving end to sample the data. The data on the
control channel contains status information on the validity of the data on the data channels, among
other useful sensor status information. Details on the LVDS timing and format can be found in section
7.3 of this document.
7.1.4 Sequencer
The on-chip sequencer will generate all required control signals to operate the sensor from only a few
external control signals. This sequencer can be activated and programmed through the SPI interface.
7.1.5 SPI Interface
The SPI interface is used to load the sequencer registers with data. The data in these registers is used
by the sequencer while driving and reading out the image sensor. Features like windowing,
subsampling, gain and offset are programmed using this interface. The data in the on-chip registers
can also be read back for test and debug of the surrounding system.
7.1.6 Temperature Sensor
A 16-bit digital temperature sensor is included in the image sensor and can be controlled by the SPI-
interface. The on-chip temperature can be obtained by reading out the register with address 127.
7.2 Operating the Sensor
This section explains how to connect and power the sensor, as well as basic recipes of how to
configure the sensor in a certain operation mode.
Information
All register values are in decimal notation unless otherwise specified.
7.2.1 Power Supplies
To power the sensor, five externally generated supplies are required (VDD18, VDD33, VDD_PIX and
VDD_RES).
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It is recommended to decouple every physical supply pin at the sensor with a 100 nF ceramic
capacitor per pin. As VDD18 and VDD_PIX draw large peak currents it is also recommended to add a
larger (>10 µF) local capacitor close to the sensor for those supplies. At the voltage regulator side,
also enough bulk decoupling has to be foreseen.
VDD18 draws its peak current every read out line. The peak current decreases with lower data rates.
Care has to be taken in the supply and decoupling design so that VDD18 is always above 1.93 V
during these peaks (so max. 50 mV dip) to guarantee sensor performance. The voltage regulator
should be able to handle the 1.7 A.
VDD_PIX draws a short but large peak current during FOT. Care has to be taken in the supply and
decoupling design so that VDD_PIX is always above 2.9 V during these peaks (so max. 100 mV dip)
to guarantee sensor performance. The peak current should be handled by the decoupling capacitors,
not the voltage regulator.
For VDD33 and VDD_RES the peak currents are lower, but still care has to be taken not allowing the
voltages dips outside the voltage range.
The voltage required is the voltage on the supplies to guarantee the best sensor performance. The
voltage range is the range the voltage should stay within (so during current peaks) to guarantee
sensor performance. If the supply is outside the voltage range, the sensor might still be functional but
performance is not guaranteed. The voltage absolute maximum is the range outside which
(permanent) sensor malfunction might occur.
For more details on the power figures and peak plots, an application note is available. This supply
needs therefore decent decoupling to dampen the current peak.
The sensor will heat up above ambient temperature (+ ~20°C/40°C idle/running at 600 MHz).
Therefore, decent system heat management is needed to keep the sensor junction temperature below
the specifications limit of 70 °C.
7.2.2 Biasing
For optimal performance, some bias pins need to be decoupled to ground or to VDD. Please refer to
the pin list for a detailed description for every pin and the appropriate decoupling.
7.2.3 Digital Input Pins
The table below gives an overview of the external pins used to operate the sensor.
Figure 11:
Digital Input Pins
Pin Name
Description
CLK_IN
Optional input clock, frequency range between 10 MHz and 60 MHz. Only needed for the
internal temperature sensor.