CMV12000_DS000603_6-00.pdf - 第77页
Document Feedback CMV12000 Application Information Datasheet • PUBLIC DS000603 • v6 - 00 • 2023 -Sep- 22 84 │ 76 9 Application Information 9.1 Color Filter For a color version of the CMV1200 0, the color filters are appl…
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CMV12000
Application Information
Datasheet • PUBLIC
DS000603 • v6-00 • 2023-Sep-22
84 │ 76
9 Application Information
9.1 Color Filter
For a color version of the CMV12000, the color filters are applied in a Bayer pattern. When flipping in
Y is not enabled (register 69 =0), the first pixel read-out, pixel (0, 0), is the top left one and has a red
filter. If register 69 is ‘2’ (recommended), the bottom left pixel (0, 3071) is read-out first and it has a
green filter.
Figure 99:
Color Filter Layout
Pixel (0,0)
R G R G
G B G B
R G R G
G B G B
R G R G
G B G B
R G R G
G B G B
Pixel (0,3071)
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CMV12000
Application Information
Datasheet • PUBLIC
DS000603 • v6-00 • 2023-Sep-22
84 │ 77
9.2 Socket
To avoid putting the sensor through the soldering heat (stressing the color filters and micro-lenses), it
is advised to use a socket and place the sensor after the soldering phase. Sockets for this device are
available from Andon Electronics (www.andonelectronics.com) in both SMD and THT configuration.
● 10-30-07(A)-237-400T4-R27-L14: THT
● 10-30-07(A)-237-414T4-R27-L14: SMD
● 10-30-07(A)-237-RB501T4-R27-L14: SMD
An optional window in the socket is possible (A) for easy access to the sensor backside. Contact
Andon Electronics directly for more information.
9.3 Pin Layout
Figure 100:
Pin Layout from Bottom View
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
H
T
_EXP2
SPI
_CLK
VDD
_PIX
VSS VDD18 VSS
OUT63
_P
OUT63
_N
VDD18 VSS
OUT56
_P
OUT56
_N
OUT52
_P
OUT52
_N
VDD18 VDD18
OUT45
_P
OUT45
_N
OUT41
_P
OUT41
_N
VDD18 VSS
OUT34
_P
OUT34
_N
VSS VDD18 DIO3
CMDP
_COMP33
CMDP
_OSC
VSS
G
FRAME
_REQ
VRAMP1
SPI
_OUT
TDIG1 TDIG2
OUT64
_P
OUT64
_N
OUT61
_P
OUT61
_N
OUT58
_P
OUT58
_N
OUT54
_P
OUT54
_N
OUT50
_P
OUT50
_N
OUT47
_P
OUT47
_N
OUT43
_P
OUT43
_N
OUT39
_P
OUT39
_N
OUT36
_P
OUT36
_N
OUTCLK
_P
OUTCLK
_N
VSS
VDD
_RES
DIO4
CMDN
_OSC
VDD
_PIX
F
SYS
_RES_N
VRAMP2
SPI
_EN
VSS VDD33 NC NC
OUT60
_P
OUT60
_N
OUT57
_P
OUT57
_N
OUT53
_P
OUT53
_N
OUT49
_P
OUT49
_N
OUT48
_P
OUT48
_N
OUT44
_P
OUT44
_N
OUT40
_P
OUT40
_N
OUT37
_P
OUT37
_N
OUT33
_P
OUT33
_N
VDD33 DIO1
CMDP
_COMP18
CMDP CMDN
E MCLK
T
_EXP1
SPI
_IN
VSS VDD33 VSS
OUT62
_P
OUT62
_N
OUT59
_P
OUT59
_N
OUT55
_P
OUT55
_N
OUT51
_P
OUT51
_N
VSS VSS
OUT46
_P
OUT46
_N
OUT42
_P
OUT42
_N
OUT38
_P
OUT38
_N
OUT35
_P
OUT35
_N
LVDS
_CLK_P
LVDS
_CLK_N
DIO2 VSS
VDD
_RES
VDD18
_PLL
D
VDD
_PIX
VSS
VDD
_PIX
VSS VDD33 VSS
OUT30
_P
OUT30
_N
OUT27
_P
OUT27
_N
OUT24
_P
OUT24
_N
OUT20
_P
OUT20
_N
OUT17
_P
OUT17
_N
OUT15
_P
OUT15
_N
OUT10
_P
OUT10
_N
OUT6
_P
OUT6
_N
OUT3
_P
OUT3
_N
VTF
_LOW1
VRES
_L
VCLAMP VDD33 VSS
CMD_COL
_PC
C
VTF
_LOW3
VBGAP VSS VDD33 VDD33
OUT32
_P
OUT32
_N
OUT28
_P
OUT28
_N
OUT25
_P
OUT25
_N
OUT21
_P
OUT21
_N
VSS VSS
OUT14
_P
OUT14
_N
OUT11
_P
OUT11
_N
OUT7
_P
OUT7
_N
OUT4
_P
OUT4
_N
CMD
_COLAMP
VTF
_LOW0
VPCH
_H
VCM
_COMP33
VTSIG
CMD
_LVDS
B
VTF
_LOW2
CMD
_RAMP
VSS VSS VSS
OUT31
_P
OUT31
_N
VSS
OUT26
_P
OUT26
_N
OUT22
_P
OUT22
_N
OUT18
_P
OUT18
_N
OUT16
_P
OUT16
_N
OUT12
_P
OUT12
_N
OUT8
_P
OUT8
_N
OUT5
_P
OUT5
_N
OUT1
_P
OUT1
_N
VSS VDD18
VREF
_ADC
VTREF
CMD_COL
_LOAD
A
VDD
_PIX
VSS VSS VDD18 VDD18 VSS
OUT29
_P
OUT29
_N
VDD18 VSS
OUT23
_P
OUT23
_N
OUT19
_P
OUT19
_N
VDD18 VDD18
OUT13
_P
OUT13
_N
OUT9
_P
OUT9
_N
VDD18 VSS
OUT2
_P
OUT2
_N
OUTCTR
_P
OUTCTR
_N
VPCH
_L
VREF TANA
CMV12000
237 µPGA Pins
(BOTTOM VIEW)
LVDS
No Pin
Not Connect
Reg/Bias/Ref
I/O
Supply
Ground