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Document Feedback CMV12000 Functional Description Datasheet • PUBLIC DS000603 • v6 - 00 • 2023 -Sep- 22 84 │ 30 By default, all 64 data output chan nels are used to transmit the image data. This mean s that two entire ro…

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CMV12000
Functional Description
Datasheet • PUBLIC
DS000603 • v6-00 • 2023-Sep-22
84 │ 29
7.3.2 Low-Level Readout Format
The data is transferred LSB first, with the transfer of bit D[0] during the high phase of the DDR output
clock. An example of 10b mode is shown below for the P-channel of one LVDS channel. T1 is the
period of the input clock (600 MHz input clock = 300 MHz output clock).
Figure 25:
10b Pixel Data on an LVDS Channel
7.3.3 Pixel Readout Format
The read-out of image data is grouped in bursts of 128 pixels per channel (2 rows at the same time via
top and bottom outputs). Each pixel is 8, 10 or 12 bits wide. For details on pixel remapping and pixel
vs. channel location please see section 7.3.4. An overhead time exists between two bursts of 128
pixels. This overhead time has the length of one pixel read-out (i.e. the length of 8, 10 or 12 bits at the
selected data rate).
Please note that depending on the bit mode (8-bit, 10-bit or 12-bit) and read-out mode (subsampling,
binning…), the actual timing of the image data may differ from one mode to another. The sections
below show the relative location of the pixel data only.
The sensor is designed to be used with both sides (bottom and top) simultaneously. There is a “one
side mode” where only one side (bottom) can be used to read out data, but binning and subsampling
in X and Y direction are not supported in this mode.
The sensor is able to send all pixel data over fewer channels. The overview of which outputs are used
when multiplexing to fewer outputs is shown below.
Figure 26:
Channel Muxing Overview
D(8) D(9) D(0) D(1) D(2) D(3) D(4) D(5) D(6) D(7) D(8) D(9) D(0) D(1) D(2) D(3)
T1
LVDS_CLOCK
_OUT
DATA_OUT
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
32 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
16 x x x x x x x x x x x x x x x x
8 x x x x x x x x
4 x x x x
2 x x
1 x
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
32 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
16 x x x x x x x x x x x x x x x x
8 x x x x x x x x
4 x x x x
2 x x
1 x
CMV12000
Functional Description
Datasheet • PUBLIC
DS000603 • v6-00 • 2023-Sep-22
84 │ 30
By default, all 64 data output channels are used to transmit the image data. This means that two entire
rows of image data are transferred (one using the top outputs and one using the bottom outputs) in
one slot of 128 pixel periods (64 × 128 = 8192). Next figure shows the timing for the top and bottom
LVDS channels. The bottom channels read out the odd rows (start at 1) and the top channels read out
the even rows.
Figure 27:
Data Output Timing with 64 (2 × 32) Channels
Only when 64 data outputs, running at 600 Mbit/s in 10b mode are used, the frame rate of 300 fps can
be achieved.
Using less output channels, this can be programmed with register 81. In this multiplexed mode, the
read-out of one row takes N × 128 periods (but two rows will be sent out at the same time). N = 1, 2, 3
… for 32, 16, 8 … channels per side. Each block of 128 pixels (=DVAL) is separated by one OH, while
each row of pixels (=LVAL) is separated by a longer OH (depending on the number of outputs and
sides, subsampling and binning).
Next figure shows the timing when multiplexing to 16 channels on each side.
Figure 28:
Data Output Timing with 2 × 16 Channels
When using the ‘one side mode’, each row is readout by the bottom outputs following the pattern in
the figure below.
Figure 29:
One Side Readout Mode with 32 (1 × 32) Channels
IDLE OH 128 OHDATA_OUT_BOTTOM 128 OH 128
Row 1 Row3 Row5
OH 128
Row7
IDLE OH 128 OHDATA_OUT_TOP 128 OH 128
Row2 Row4 Row6
2x32CH
OH 128
Row8
IDLE OH 128 OH
DATA_OUT_TOP
128 OH 128
Row2 Row4
OH 128 OH 128 OH 128
Row6
2x16CH
OH 128 OH 128
Row8
IDLE OH 128 OHDATA_OUT_BOTTOM 128 OH 128
Row 1 Row3
OH 128 OH 128 OH 128
Row5
OH 128 OH 128
Row7
IDLE OH 128 OHDATA_OUT_BOTTOM 128 OH 128
Row 1 Row 2 Row 4
1x32CH
OH 128
Row 3
CMV12000
Functional Description
Datasheet • PUBLIC
DS000603 • v6-00 • 2023-Sep-22
84 │ 31
7.3.4 Pixel Remapping
Depending on the number of output channels, the pixels are located at different channels and are read
out at a different moment in time. With the details from the next sections, the end user is able to remap
the pixels on the outputs to their correct image array location.
Two Sided Readout Mode
Below are two examples of the pixel mapping when using 2 × 32 channels and 2 × 16 channels. It will
be similar for less channels.
64 bursts (2 × 32) of 128 pixels happen in parallel on the data outputs. This means that two complete
rows are read out in one burst; the odd rows via the bottom channels, the even rows via the top
channels. The amount of rows that will be read out depends on the value in the corresponding
register. By default there are 3072 rows read out.
Figure 30:
Pixel Mapping Using 2 x 32 Channels
When 2 × 16 output mode is used, the pixel data is placed on the outputs as detailed in the figure
below. 16 bursts of 128 pixels happen in parallel on the data outputs on both sides simultaneous (16
on the top and 16 on the bottom outputs); the odd rows via the bottom channels, the even rows via the
top channels. This means that one complete row one each side is read out in two burst (so effectively
two rows are read-out in two bursts).
The time needed to read out two rows is doubled compared to when 64 outputs are used. The even
LVDS channels are not being used in this case, so they can be turned off by setting the correct bits in
IDLE Pixel 0 to 127Channel 1
IDLEChannel 2
Row 1
Pixel 128 to 255
IDLEChannel 31 Pixel 3840 to 3967
IDLEChannel 32 Pixel 3968 to 4095
Pixel 0 to 127
Row 3
Pixel 128 to 255
Pixel 3840 to 3967
Pixel 3968 to 4095
IDLE Pixel 0 to 127Channel 33
IDLEChannel 34
Row 2
Pixel 128 to 255
IDLEChannel 63 Pixel 3840 to 3967
IDLE
Channel 64
Pixel 3968 to 4095
Pixel 0 to 127
Row 4
Pixel 128 to 255
Pixel 3840 to 3967
Pixel 3968 to 4095
2x32CH