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Document Feedback CMV12000 Functional Description Datasheet • PUBLIC DS000603 • v6 - 00 • 2023 -Sep- 22 84 │ 22 Pin Name Description LVDS_CLK_P/N Input clock, frequency range between 100 MHz and 600 MHz, depe nding on th…

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CMV12000
Functional Description
Datasheet • PUBLIC
DS000603 • v6-00 • 2023-Sep-22
84 │ 21
It is recommended to decouple every physical supply pin at the sensor with a 100 nF ceramic
capacitor per pin. As VDD18 and VDD_PIX draw large peak currents it is also recommended to add a
larger (>10 µF) local capacitor close to the sensor for those supplies. At the voltage regulator side,
also enough bulk decoupling has to be foreseen.
VDD18 draws its peak current every read out line. The peak current decreases with lower data rates.
Care has to be taken in the supply and decoupling design so that VDD18 is always above 1.93 V
during these peaks (so max. 50 mV dip) to guarantee sensor performance. The voltage regulator
should be able to handle the 1.7 A.
VDD_PIX draws a short but large peak current during FOT. Care has to be taken in the supply and
decoupling design so that VDD_PIX is always above 2.9 V during these peaks (so max. 100 mV dip)
to guarantee sensor performance. The peak current should be handled by the decoupling capacitors,
not the voltage regulator.
For VDD33 and VDD_RES the peak currents are lower, but still care has to be taken not allowing the
voltages dips outside the voltage range.
The voltage required is the voltage on the supplies to guarantee the best sensor performance. The
voltage range is the range the voltage should stay within (so during current peaks) to guarantee
sensor performance. If the supply is outside the voltage range, the sensor might still be functional but
performance is not guaranteed. The voltage absolute maximum is the range outside which
(permanent) sensor malfunction might occur.
For more details on the power figures and peak plots, an application note is available. This supply
needs therefore decent decoupling to dampen the current peak.
The sensor will heat up above ambient temperature (+ ~20°C/40°C idle/running at 600 MHz).
Therefore, decent system heat management is needed to keep the sensor junction temperature below
the specifications limit of 70 °C.
7.2.2 Biasing
For optimal performance, some bias pins need to be decoupled to ground or to VDD. Please refer to
the pin list for a detailed description for every pin and the appropriate decoupling.
7.2.3 Digital Input Pins
The table below gives an overview of the external pins used to operate the sensor.
Figure 11:
Digital Input Pins
Pin Name
Description
CLK_IN
Optional input clock, frequency range between 10 MHz and 60 MHz. Only needed for the
internal temperature sensor.
CMV12000
Functional Description
Datasheet • PUBLIC
DS000603 • v6-00 • 2023-Sep-22
84 │ 22
Pin Name
Description
LVDS_CLK_P/N
Input clock, frequency range between 100 MHz and 600 MHz, depending on the bit mode.
SYS_RES_N
System reset pin, active low signal. Resets the on-board sequencer and must be kept low
during start-up.
FRAME_REQ
Frame request pin. When a high state is detected on this pin, the programmed number of
frames is captured and sent by the sensor. The pulse should be at least 8, 10 or 12 * LVDS
input clock periods wide to be detected, depending on the used bit mode.
SPI_IN
Data input pin for the SPI interface. The data to program the image sensor is sent over this
pin.
SPI_EN
SPI enable pin. When this pin is high, the data should be written/read on the SPI.
SPI_CLK
SPI clock. This is the clock on which the SPI runs (max 30 MHz).
T_EXP1
Input pin, which can be used to program the exposure time externally. The pulse should be
at least 8, 10 or 12 * LVDS input clock periods wide to be detected, depending on the used
bit mode. Optional.
T_EXP2
Input pin, which can be used to program the exposure time externally in interleaved high
dynamic range mode. The pulse should be at least 8, 10 or 12 * LVDS input clock periods
wide to be detected, depending on the used bit mode. Optional.
7.2.4 Clocking
The LVDS input clock defines the output data rate of the CMV12000. The maximum data rate of the
output is 600 Mbit/s (DDR 300 MHz output clock) which results in an input LVDS_CLK clock of
600 MHz. The minimum LVDS_CLK_P/N frequency is 100 MHz for 12-bit, 10-bit and 8-bit. At lower
frequencies, image performance will decrease. Any input frequency (min < f < max) applied (in MHz)
will result in a corresponding output data rate (in Mbit/s). Some register settings need to be changed
when changing the input clock frequency from 600 MHz. See section 7.7.4.
7.2.5 Startup Sequence
The following sequence should be followed when the device is started up:
Figure 12:
Startup Sequence
1μs
1μs
Stable time
Supply
LVDS_CLK
SYS_RES_N
FRAME_REQ
CMV12000
Functional Description
Datasheet • PUBLIC
DS000603 • v6-00 • 2023-Sep-22
84 │ 23
The LVDS input clock should only start after the rise time of the supplies. The external reset pin
should be released at least 1 μs after the supplies have become stable. The first frame can be
requested 1 μs after the reset pin has been released. An optional SPI upload (to program the
sequencer) is possible 1 μs after the reset pin has been released. In this case, the FRAME_REQ
pulse must be postponed until after the SPI upload has been completed.
7.2.6 Reset Sequence
If a sensor reset is necessary while the sensor is running, the next sequence should be followed:
Figure 13:
Reset Sequence
The on-board sequencer will be reset and all programming registers will return to their default start-up
values when a falling edge is detected on the SYS_RES_N pin. After the reset there is a minimum
time of 1 μs needed, before a FRAME_REQ pulse can be sent.
When a switch from 12-bit to 10-bit or 8-bit mode (or vice versa) is necessary, the following sequence
should be followed:
Figure 14:
Reset Sequence with Changing Bit Mode
The following SPI register should be uploaded in this mode: Bit_mode (address 118): set to desired bit
resolution mode.
1μs
LVDS_CLK
SYS_RES_N
FRAME_REQ
1μs
LVDS_CLK
SYS_RES_N
FRAME_REQ
Bit mode settings
SPI upload
1μs