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Document Feedback CMV12000 Functional Description Datasheet • PUBLIC DS000603 • v6 - 00 • 2023 -Sep- 22 84 │ 60 7.6 Additional Features 7.6.1 Offset A digital offset can be applied t o the output signal. This dark level …
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CMV12000
Functional Description
Datasheet • PUBLIC
DS000603 • v6-00 • 2023-Sep-22
84 │ 59
Reg. Name
Address
Bits
Default
Description
ADC_range_mult
116
[9:8]
1
Change multiplier of the slope and the input range of the
ramp used by the ADC
0: 8b (x1)
1: 10b (x2)
3: 12b (x4)
ADC_range_mult2
100
[1:0]
0
Change multiplier of the slope and the input range of the
ramp used by the ADC for lower clock speeds. Only use
with ADC_range_mult=3.
0: x4
1: x8
3: x16
The ADC range also has to be adjusted when using different clock speeds. See section 7.7.4.
7.5.4 Data Rate
During start-up or after a sequencer reset, the data rate can be changed if a lower speed than
600 Mbit/s is desired. This can be done by applying a lower LVDS input clock (LVDS_CLK_P/N).
7.5.5 Power Consumption
The power consumption of the sensor can be decreased by disabling the LVDS data channels when
they are not used (in 32, 16, 8, 4, 2 or 1 channel(s) mode). Disabling an output saves about 15 mW on
the VDD18 supply per output.
Figure 80:
Power Consumption
Reg. Name
Address
Bits
Default
Description
Channel_en_bot
90
91
[15:0]
[15:0]
65535
Sets 1 channel per bit for the bottom outputs
0: Disabled
1: Enabled
Channel_en_top
92
93
[15:0]
[15:0]
65535
Sets 1 channel per bit for the top outputs
0: Disabled
1: Enabled
Channel_en
94
[2:0]
7
Bit 0: Output clock channel
Bit 1: Control channel
Bit 2: Input clock channel
0: Disabled
1: Enabled
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CMV12000
Functional Description
Datasheet • PUBLIC
DS000603 • v6-00 • 2023-Sep-22
84 │ 60
7.6 Additional Features
7.6.1 Offset
A digital offset can be applied to the output signal. This dark level offset can be programmed by setting
the desired value in the sequencer registers. A bottom and top channel offset can be given to the dark
level by programming the appropriate registers. This offset should be adjusted per device and per bit
mode to get the desired dark level.
Figure 81:
Offset Settings
Reg. Name
Address
Bits
Default
Description
Offset_bot
87
[11:0]
780
Sets the relative offset of the dark level for the bottom
outputs following a 2’s-complement code.
1815: 12b
510: 10b
520: 8b
Offset_top
88
[11:0]
780
Sets the relative offset of the dark level for the top
outputs following a 2’s-complement code.
1815: 12b
510: 10b
520: 8b
7.6.2 Gain
An analog (using a Programmable Gain Amplifier) and digital gain (after ADC) can be applied to the
image. The digital gain has to be adjusted based on the bit mode for a unity gain.
Figure 82:
Gain Settings
Reg. Name
Address
Bits
Default
Description
PGA_gain
115
[2:0]
0
0: x1
1: x2
3: x3
7: x4
PGA_div
115
[3]
0
Can be used in binning mode
0: Divide by 1
1: Divide by 3
Dig_gain
117
[4:0]
4
Set to 1,2,3,4,6,8,10,12,14,16 to get the appropriate
digital gain. For unity gain use:
1: 12b
4: 10b
6: 8b
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CMV12000
Functional Description
Datasheet • PUBLIC
DS000603 • v6-00 • 2023-Sep-22
84 │ 61
7.6.3 Electrical Black Reference Columns
The first and last eight columns of the pixel array can be changed to an electrical black reference. This
electrical black reference can be used to correct row noise. The black level offset between the EB and
normal pixels will differ. Because of the limited amount of EB pixels per row (16), row correction is
limited.
Figure 83:
Electrical Black Reference Settings
Reg. Name
Address
Bits
Default
Description
Black_col_en
89
[15]
0
0: Off
1: On
7.6.4 Test Pattern
The sensor has a built-in digital fixed test pattern. This can be used, for example, to test the FPGA’s
data input implementation.
The pattern consists of increasing pixel values per column per channel. The first column of each (top
and bottom) channel, offsets with 1 compared to the previous channel. So channels 1/33 will contain
0, 1, 2 … 126, 127 and channels 2/34 contain 1, 2, 3 … 127, 128 and channels 32/64 contain 31, 32,
33 … 157, 158 and so on.
To have the same test pattern in 8b as in 10b and 12b, the digital gain has to be set to 16. Set it back
to 6 when taking normal images again.
Figure 84:
Test Pattern Setting
Reg. Name
Address
Bits
Default
Description
Test
122
[1:0]
0
0: Off
3: On
Figure 85:
Test Pattern Image