CMV12000_DS000603_6-00.pdf - 第12页

Document Feedback CMV12000 Pin Assignment Datasheet • PUBLIC DS000603 • v6 - 00 • 2023 -Sep- 22 84 │ 11 Number Name Type Description F22 OUT60_N LVDS output LVDS negative output channel 60 F23 OUT60_P LVDS output LVDS po…

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CMV12000
Pin Assignment
Datasheet • PUBLIC
DS000603 • v6-00 • 2023-Sep-22
84 │ 10
Number
Name
Type
Description
E12
OUT42_P
LVDS output
LVDS positive output channel 42
E13
OUT46_N
LVDS output
LVDS negative output channel 46
E14
OUT46_P
LVDS output
LVDS positive output channel 46
E15
GND
Ground
Ground pin
E16
GND
Ground
Ground pin
E17
OUT51_N
LVDS output
LVDS negative output channel 51
E18
OUT51_P
LVDS output
LVDS positive output channel 51
E19
OUT55_N
LVDS output
LVDS negative output channel 55
E20
OUT55_P
LVDS output
LVDS positive output channel 55
E21
OUT59_N
LVDS output
LVDS negative output channel 59
E22
OUT59_P
LVDS output
LVDS positive output channel 59
E23
OUT62_N
LVDS output
LVDS negative output channel 62
E24
OUT62_P
LVDS output
LVDS positive output channel 62
E25
GND
Ground
Ground pin
E26
VDD33
Supply
3.3 V supply
E27
GND
Ground
Ground pin
E28
SPI_IN
Digital input
SPI data input pin
E29
T_EXP2
Digital input
Input pin for external exposure
E30
CLK_IN
Digital input
Master input clock
F1
CMDN
Bias
Decouple with 100 nF to GND
F2
CMDP
Bias
Decouple with 100 nF to VDD33
F3
CMDP_COMP18
Bias
Decouple with 100 nF to VDD33
F4
DIO1
Ground
Connect to ground
F5
VDD33
Supply
3.3 V supply
F6
OUT33_N
LVDS output
LVDS negative output channel 33
F7
OUT33_P
LVDS output
LVDS positive output channel 33
F8
OUT37_N
LVDS output
LVDS negative output channel 37
F9
OUT37_P
LVDS output
LVDS positive output channel 37
F10
OUT40_N
LVDS output
LVDS negative output channel 40
F11
OUT40_P
LVDS output
LVDS positive output channel 40
F12
OUT44_N
LVDS output
LVDS negative output channel 44
F13
OUT44_P
LVDS output
LVDS positive output channel 44
F14
OUT48_N
LVDS output
LVDS negative output channel 48
F15
OUT48_P
LVDS output
LVDS positive output channel 48
F16
OUT49_N
LVDS output
LVDS negative output channel 49
F17
OUT49_P
LVDS output
LVDS positive output channel 49
F18
OUT53_N
LVDS output
LVDS negative output channel 53
F19
OUT53_P
LVDS output
LVDS positive output channel 53
F20
OUT57_N
LVDS output
LVDS negative output channel 57
F21
OUT57_P
LVDS output
LVDS positive output channel 57
CMV12000
Pin Assignment
Datasheet • PUBLIC
DS000603 • v6-00 • 2023-Sep-22
84 │ 11
Number
Name
Type
Description
F22
OUT60_N
LVDS output
LVDS negative output channel 60
F23
OUT60_P
LVDS output
LVDS positive output channel 60
F24
NC
Not connected
F25
NC
Not connected
F26
VDD33
Supply
3.3 V supply
F27
GND
Ground
Ground pin
F28
SPI_EN
Digital input
SPI enable input pin
F29
VRAMP2
Bias
Start voltage second ramp (decouple with 100 nF to GND)
F30
SYS_RES_N
Digital input
Input pin for sequencer reset
G1
VDD_PIX
Supply
3.0 V supply
G2
CMDN_OSC
Bias
Decouple with 100 nF to GND
G3
DIO4
Ground
Connect to ground
G4
VDD_RES
Supply
3.3 V supply
G5
GND
Ground
Ground pin
G6
OUTCLK_N
LVDS output
LVDS negative clock output signal
G7
OUTCLK_P
LVDS output
LVDS positive clock output signal
G8
OUT36_N
LVDS output
LVDS negative output channel 36
G9
OUT36_P
LVDS output
LVDS positive output channel 36
G10
OUT39_N
LVDS output
LVDS negative output channel 39
G11
OUT39_P
LVDS output
LVDS positive output channel 39
G12
OUT43_N
LVDS output
LVDS negative output channel 43
G13
OUT43_P
LVDS output
LVDS positive output channel 43
G14
OUT47_N
LVDS output
LVDS negative output channel 47
G15
OUT47_P
LVDS output
LVDS positive output channel 47
G16
OUT50_N
LVDS output
LVDS negative output channel 50
G17
OUT50_P
LVDS output
LVDS positive output channel 50
G18
OUT54_N
LVDS output
LVDS negative output channel 54
G19
OUT54_P
LVDS output
LVDS positive output channel 54
G20
OUT58_N
LVDS output
LVDS negative output channel 58
G21
OUT58_P
LVDS output
LVDS positive output channel 58
G22
OUT61_N
LVDS output
LVDS negative output channel 61
G23
OUT61_P
LVDS output
LVDS positive output channel 61
G24
OUT64_N
LVDS output
LVDS negative output channel 64
G25
OUT64_P
LVDS output
LVDS positive output channel 64
G26
TDIG2
Digital output
Test pin for digital sequencer signals (do not connect)
G27
TDIG1
Digital output
Test pin for digital sequencer signals (do not connect)
G28
SPI_OUT
Digital output
SPI data output pin
G29
VRAMP1
Bias
Start voltage first ramp (decouple with 100 nF to GND)
G30
FRAME_REQ
Digital input
Frame request pin
H1
GND
Ground
Ground pin
CMV12000
Pin Assignment
Datasheet • PUBLIC
DS000603 • v6-00 • 2023-Sep-22
84 │ 12
Number
Name
Type
Description
H2
CMDP_OSC
Bias
Decouple with 100 nF to VDD18
H3
CMDP_COMP33
Bias
Decouple with 100 nF to VDD33
H4
DIO3
Ground
Connect to ground
H5
VDD18
Supply
1.98 V supply
H6
GND
Ground
Ground pin
H7
OUT34_N
LVDS output
LVDS negative output channel 34
H8
OUT34_P
LVDS output
LVDS positive output channel 34
H9
GND
Ground
Ground pin
H10
VDD18
Supply
1.98 V supply
H11
OUT41_N
LVDS output
LVDS negative output channel 41
H12
OUT41_P
LVDS output
LVDS positive output channel 41
H13
OUT45_N
LVDS output
LVDS negative output channel 45
H14
OUT45_P
LVDS output
LVDS positive output channel 45
H15
VDD18
Supply
1.98 V supply
H16
VDD18
Supply
1.98 V supply
H17
OUT52_N
LVDS output
LVDS negative output channel 52
H18
OUT52_P
LVDS output
LVDS positive output channel 52
H19
OUT56_N
LVDS output
LVDS negative output channel 56
H20
OUT56_P
LVDS output
LVDS positive output channel 56
H21
GND
Ground
Ground pin
H22
VDD18
Supply
1.98 V supply
H23
OUT63_N
LVDS output
LVDS negative output channel 63
H24
OUT63_P
LVDS output
LVDS positive output channel 63
H25
GND
Ground
Ground pin
H26
VDD18
Supply
1.98 V supply
H27
GND
Ground
Ground pin
H28
VDD_PIX
Supply
3.0 V supply
H29
SPI_CLK
Digital input
SPI clock input pin
H30
T_EXP1
Digital input
Input pin for external exposure