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Document Feedback CMV12000 Functional Description Datasheet • PUBLIC DS000603 • v6 - 00 • 2023 -Sep- 22 84 │ 59 Reg. Name Address Bits Default Description ADC_range_mult 116 [9:8] 1 Change multiplier of the slope an d th…
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CMV12000
Functional Description
Datasheet • PUBLIC
DS000603 • v6-00 • 2023-Sep-22
84 │ 58
Attention
Subsampling and binning are not supported when only using one side readout
7.5.2 Training Pattern
As detailed in section 7.3.6, a training pattern is sent over the LVDS data channels whenever no valid
image data is sent. The training pattern TP1 can be programmed using the sequencer register below.
Figure 77:
Training Pattern
Reg. Name
Address
Bits
Default
Description
Training_pattern
89
[11:0]
85
Sets the training pattern value.
7.5.3 Bit Mode
The CMV12000 has the possibility to send 12 bits, 10 bits or 8 bits per pixel. The end user can select
the desired resolution by programming the corresponding sequencer register. See section 7.2.6 for
details on how the bit mode can be changed. See section 7.7 for additional required register settings.
Figure 78:
Bit Mode Setting
Reg. Name
Address
Bits
Default
Description
Bit_mode
118
[1:0]
1
0: 12b (12 bits per pixel)
1: 10b (10 bits per pixel)
2: 8b (8 bits per pixel)
When changing the bit mode of the ADC, the ADC input range also has to be modified so the analog
pixel voltage is in the correct range of the ADC input.
Figure 79:
ADC Range Settings
Reg. Name
Address
Bits
Default
Description
ADC_range
116
[7:0]
127
Change the slope and the input range of the ramp used
by the ADC
205: 8b
165: 10b
230: 12b
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CMV12000
Functional Description
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84 │ 59
Reg. Name
Address
Bits
Default
Description
ADC_range_mult
116
[9:8]
1
Change multiplier of the slope and the input range of the
ramp used by the ADC
0: 8b (x1)
1: 10b (x2)
3: 12b (x4)
ADC_range_mult2
100
[1:0]
0
Change multiplier of the slope and the input range of the
ramp used by the ADC for lower clock speeds. Only use
with ADC_range_mult=3.
0: x4
1: x8
3: x16
The ADC range also has to be adjusted when using different clock speeds. See section 7.7.4.
7.5.4 Data Rate
During start-up or after a sequencer reset, the data rate can be changed if a lower speed than
600 Mbit/s is desired. This can be done by applying a lower LVDS input clock (LVDS_CLK_P/N).
7.5.5 Power Consumption
The power consumption of the sensor can be decreased by disabling the LVDS data channels when
they are not used (in 32, 16, 8, 4, 2 or 1 channel(s) mode). Disabling an output saves about 15 mW on
the VDD18 supply per output.
Figure 80:
Power Consumption
Reg. Name
Address
Bits
Default
Description
Channel_en_bot
90
91
[15:0]
[15:0]
65535
Sets 1 channel per bit for the bottom outputs
0: Disabled
1: Enabled
Channel_en_top
92
93
[15:0]
[15:0]
65535
Sets 1 channel per bit for the top outputs
0: Disabled
1: Enabled
Channel_en
94
[2:0]
7
Bit 0: Output clock channel
Bit 1: Control channel
Bit 2: Input clock channel
0: Disabled
1: Enabled
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Functional Description
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7.6 Additional Features
7.6.1 Offset
A digital offset can be applied to the output signal. This dark level offset can be programmed by setting
the desired value in the sequencer registers. A bottom and top channel offset can be given to the dark
level by programming the appropriate registers. This offset should be adjusted per device and per bit
mode to get the desired dark level.
Figure 81:
Offset Settings
Reg. Name
Address
Bits
Default
Description
Offset_bot
87
[11:0]
780
Sets the relative offset of the dark level for the bottom
outputs following a 2’s-complement code.
1815: 12b
510: 10b
520: 8b
Offset_top
88
[11:0]
780
Sets the relative offset of the dark level for the top
outputs following a 2’s-complement code.
1815: 12b
510: 10b
520: 8b
7.6.2 Gain
An analog (using a Programmable Gain Amplifier) and digital gain (after ADC) can be applied to the
image. The digital gain has to be adjusted based on the bit mode for a unity gain.
Figure 82:
Gain Settings
Reg. Name
Address
Bits
Default
Description
PGA_gain
115
[2:0]
0
0: x1
1: x2
3: x3
7: x4
PGA_div
115
[3]
0
Can be used in binning mode
0: Divide by 1
1: Divide by 3
Dig_gain
117
[4:0]
4
Set to 1,2,3,4,6,8,10,12,14,16 to get the appropriate
digital gain. For unity gain use:
1: 12b
4: 10b
6: 8b