IPC-7351-2005_表面贴装焊盘布局设计和标准通用要求.pdf - 第10页

ｗｗｗ．ｂｚｆｘｗ．ｃｏｍ T able 3-17 Conductor Width T olerances, 0.046 mm [0.00181 in] Copper , mm [in] ............................ 28 T able 3-18 Feature Location Accuracy (units: mm [in]) ...... 28 T able 6-1 Printed Board Stru…

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Figure 3-12 Use of Vias in High Component Density

Printed Circuit Boards .................................... 25

Figure 3-13 Conductor Routing Capability Test Pattern .... 25

Figure 3-14 Land Pattern to Via Relationship .................... 26

Figure 3-15 Examples of Via Positioning Concepts .......... 26

Figure 3-16 Vias Under Components ................................ 27

Figure 3-17 Conductor Description .................................... 28

Figure 3-18 Examples of Modiﬁed Landscapes ................ 28

Figure 3-19 Typical Copper Glass Laminate Panel ........... 29

Figure 3-20 Conductor Clearance for V-Groove Scoring .. 30

Figure 3-21 Breakaway (Routed Pattern) with

Routed Slots ................................................... 31

Figure 3-22 Gang Solder Mask Window ............................ 31

Figure 3-23 Pocket Solder Mask Window ......................... 31

Figure 4-1 Component Operating Temperature Limits .... 32

Figure 5-1 Test Via Grid Concepts ................................... 34

Figure 5-2 General Relationship Between Test

Contact Size and Test Probe Misses ............. 35

Figure 5-3 Test Probe Feature Distance from

Component ..................................................... 36

Figure 7-1 Typical Process Flow for Full Surface

Mount Type 1b and 2b Surface Mount

Technology ...................................................... 40

Figure 7-2 Assembly Process Flow for Two-Side

Surface Mount with PIH ................................. 41

Figure 8-1 Packaging of Discrete Components ............... 44

Figure 8-2 Chip Resistor Construction ............................. 45

Figure 8-3 Chip Capacitor Construction .......................... 46

Figure 8-4 Inductor Construction ..................................... 46

Figure 8-5 Tantalum Capacitor Construction ................... 46

Figure 8-6 Metal Electrode Face Component

Construction .................................................... 47

Figure 8-7 Break-Away Diagram of MELF

Components ................................................... 47

Figure 8-8 SOT 23 Construction ...................................... 47

Figure 8-9 SOT 89 Construction ...................................... 48

Figure 8-10 SOD 123 Construction ................................... 48

Figure 8-11 SOT143 Construction ..................................... 48

Figure 8-12 SOT 223 Construction .................................... 49

Figure 8-13 TO252 (DPAK Type) Construction ................. 49

Figure 9-1 SOIC Construction .......................................... 50

Figure 9-2 SOP8/SOP63 Construction ............................ 50

Figure 9-3 SOP127 Construction ..................................... 51

Figure 9-4 TSSOP Construction ...................................... 51

Figure 9-5 CFP127 Construction ..................................... 51

Figure 10-1 SOJ Construction ........................................... 52

Figure 11-1 BQFP Construction ......................................... 53

Figure 11-2 SQFP and QFP Construction ......................... 53

Figure 11-3 QFPR Construction ........................................ 54

Figure 11-4 CQFP Construction ......................................... 54

Figure 12-1 PLCC Construction ......................................... 55

Figure 12-2 PLCCR Construction ...................................... 56

Figure 13-1

DIP Construction ............................................ 56

Figure 14-1

Ball Grid Array (BGA) IC Package Example .. 57

Figure 14-2 Example of Plastic BGA Package

Conﬁgurations ................................................. 57

Figure 14-3 Ceramic Column Grid Array (CGA)

Package (Cross-Sectional View) .................... 58

Figure 14-4

Bottom View of BGA Devices ......................... 59

Figure 14-5

One Package Size, Two Full Matrices ........... 59

Figure 14-6 Perimeter and Thermally Enhanced

Matrices .......................................................... 60

Figure 14-7

Staggered Matrix ............................................ 60

Figure 14-8

Selective Depopulation ................................... 60

Figure 14-9

Device Orientation and Contact A1 Position .. 61

Figure 15-1

Quad Flat No-Lead (QFN) Construction ........ 63

Figure 15-2 Quad Flat No-Lead (QFN) Construction

(Cross-Sectional View) ................................... 64

Figure 15-3

Small Outline No-Lead (SON) Construction .. 64

Figure 16-1 Zero Component Rotations for Common

Package Outlines ........................................... 66

Figure A-1 General Description of Process Validation

Contact Pattern and Interconnect .................. 71

Figure A-2 Photoimage of IPC-A-49 Test Board for

Primary Side ................................................... 72

Tables

Table 3-1 Tolerance Analysis Elements for Chip

Devices .............................................................. 11

Table 3-2 Flat Ribbon L and Gull-Wing Leads

(greater than 0.625 mm pitch) (unit: mm) ......... 12

Table 3-3 Flat Ribbon L and Gull-Wing Leads (less

than or equal to 0.625 mm pitch) (unit: mm) .... 12

Table 3-4

J Leads (unit: mm) ............................................ 13

Table 3-5 Rectangular or Square-End Components

(Capacitors and Resistors) Equal to or Larger

than 1608 (0603) (unit: mm) ............................. 13

Table 3-6 Rectangular or Square-End Components

(Capacitors and Resistors) Smaller than

1608 (0603) (unit: mm) ..................................... 13

Table 3-7 Cylindrical End Cap Terminations (MELF)

(unit: mm) .......................................................... 13

Table 3-8

Bottom Only Terminations (unit: mm) ............... 13

Table 3-9 Leadless Chip Carrier with Castellated

Terminations (unit: mm) .................................... 13

Table 3-10

Butt Joints (unit: mm) ........................................ 14

Table 3-11 Inward Flat Ribbon L and Gull-Wing Leads

(Tantalum Capacitors) (unit: mm) ..................... 14

Table 3-12

Flat Lug Leads (unit: mm) ................................. 14

Table 3-13

Flat, No Lead (unit: mm) ................................... 14

Table 3-14

Small Outline (SO), No-Lead (unit: mm) .......... 14

Table 3-15

IPC-7351 Land Pattern Naming Convention .... 16

Table 3-16 Product Categories and Worst-Case

Use Environments for Surface Mounted

Electronics (For Reference Only) ..................... 19

February 2005 IPC-7351

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Table 3-17 Conductor Width Tolerances, 0.046 mm

[0.00181 in] Copper, mm [in] ............................ 28

Table 3-18 Feature Location Accuracy (units: mm [in]) ...... 28

Table 6-1 Printed Board Structure Comparison ................ 37

Table 6-2 PCB Structure Selection Considerations .......... 38

Table 6-3 PCB Structure Material Properties .................... 38

Table 14-1 JEDEC Standard JEP95 Allowable Ball

Diameter Variations for FBGA (mm) ................. 58

Table 14-2 Ball Diameter Sizes (mm) ................................. 61

Table 14-3 Land Approximation (mm) ................................. 62

Table 14-4 BGA Variation Attributes (mm) .......................... 62

Table 14-5 Land-to-Ball Calculations for Current and

Future BGA Packages (mm) ............................. 62

IPC-7351 February 2005

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Generic Requirements for Surface

Mount Design and Land Pattern Standard

1 SCOPE

This document provides information on land pattern geom-

etries used for the surface attachment of electronic compo-

nents. The intent of the information presented herein is to

provide the appropriate size, shape and tolerance of surface

mount land patterns to insure sufficient area for the appro-

priate solder ﬁllet to meet the requirements of IPC/EIA

J-STD-001, and also to allow for inspection, testing, and

rework of those solder joints.

1.1 Purpose Although, in many instances, the land pat-

tern geometries can be different based on the type of sol-

dering used to attach the electronic part, wherever possible,

land patterns are deﬁned with consideration to the attach-

ment process being used. Designers can use the informa-

tion contained herein to establish standard conﬁgurations

not only for manual designs but also for computer-aided

design systems. Whether parts are mounted on one or both

sides of the board, subjected to wave, reﬂow, or other type

of soldering, the land pattern and part dimensions should

be optimized to insure proper solder joint and inspection

criteria.

Land patterns are dimensionally deﬁned and are a part of

the printed board circuitry geometry, as they are subject to

the producibility levels and tolerances associated with plat-

ing, etching, assembly or other conditions. The producibil-

ity aspects also pertain to the use of solder mask and the

registration required between the solder mask and the con-

ductor patterns.

Note 1: The dimensions used for component descriptions

have been extracted from standards developed by industrial

and/or standards bodies. Designers should refer to these

standards for additional or speciﬁc component package

dimensions.

Note 2: For a comprehensive description of the given

printed board and for achieving the best possible solder

joints to the devices assembled, the whole set of design

elements includes, beside the land pattern deﬁnition:

• Soldermask.

• Solder paste stencil.

• Clearance between adjacent components.

• Clearance between bottom of component and PCB sur-

face, if relevant.

• Keepout areas, if relevant.

• Suitable rules for adhesive applications.

The whole of design elements is commonly deﬁned as

‘‘mounting conditions.’’ This standard deﬁnes land patterns

and includes recommendations for clearances between

adjacent components and for other design elements.

Note 3: Elements of the mounting conditions, particularly

the courtyard, given in this standard are related to the

reﬂow soldering process. Adjustments for wave or other

soldering processes, if applicable, have to be carried out by

the user. This may also be relevant when solder alloys

other than eutectic tin lead solders are used.

Note 4: This standard assumes that the land pattern fol-

lows the principle that, even under worst case conditions,

the overlap of the component termination and the corre-

sponding soldering land will be complete.

Note 5: Heat dissipation aspects have not been taken into

account in this standard. Greater mass may require slower

process speed to allow heat transfer.

Note 6: Heavier components (greater weight per land)

require larger lands; thus, adding additional land pattern

surface will increase surface area of molten solder to

enhance capabilities of extra weight. In some cases the

lands shown in the standard may not be large enough; in

these cases, considering additional measures may be neces-

sary.

Note 7: The land form may be rectangular with straight or

rounded corners. In the latter case the area of the smallest

circumscribed rectangle shall be equal to that of one with

straight corners.

1.2 Documentation Hierarchy This standard identiﬁes

the generic physical design principles involved in the

creation of land patterns for surface mount components,

and is supplemented by a shareware IPC-7351 Land Pat-

tern viewer that provides, through the use of a graphical

user interface, the individual component dimensions and

corresponding land pattern recommendations based upon

families of components. The IPC-7351 Land Pattern

Viewer is provided on CD-ROM as part of the IPC-7351.

Updates to land pattern dimensions, including patterns for

new component families, can be found on the IPC website

(www.ipc.org) under ‘‘PCB Tools and Calculators.’’ See

Appendix C for more information on the IPC-7351 Land

Pattern Viewer.

February 2005 IPC-7351