IPC-7351-2005_表面贴装焊盘布局设计和标准通用要求.pdf - 第9页
ｗｗｗ．ｂｚｆｘｗ．ｃｏｍ Figure 3-12 Use of Vias in High Component Density Printed Circuit Boards .................................... 25 Figure 3-13 Conductor Routing Capability T est Pattern .... 25 Figure 3-14 Land Pattern to Vi…
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9.4.3 Resistance to Soldering ..................................... 51
9.5 CFP127 ............................................................... 51
9.5.1 Marking .............................................................. 51
9.5.2 Carrier Packages Format ................................... 51
9.5.3 Resistance to Soldering ..................................... 52
10 IPC-7354 J-LEADED COMPONENTS,
TWO SIDES
.......................................................... 52
10.1 Basic Construction ............................................. 52
10.2 Marking .............................................................. 52
10.3 Carrier Package Format ..................................... 52
10.4 Process Considerations ...................................... 52
11 IPC-7355 GULL-WING LEADED
COMPONENTS, FOUR SIDES
............................. 52
11.1 BQFP (PQFP) .................................................... 53
11.1.1 Carrier Package Format ..................................... 53
11.2 SQFP/QFP .......................................................... 53
11.2.1 Carrier Package Format ..................................... 53
11.3 QFPR .................................................................. 54
11.3.1 Carrier Package Format ..................................... 54
11.4
CQFP .................................................................. 54
11.4.1
Carrier Package Format ..................................... 54
12 IPC-7356 J LEADED COMPONENTS,
FOUR SIDES
......................................................... 54
12.1
PLCC .................................................................. 55
12.1.1
Premolded Plastic Chip Carriers ....................... 55
12.1.2
Postmolded Plastic Chip Carriers ..................... 55
12.2
PLCCR ............................................................... 55
12.2.1
Premolded Plastic Chip Carriers ....................... 56
12.2.2
Postmolded Plastic Chip Carriers ..................... 56
13 IPC-7357 POST (DIP) LEADS, TWO SIDES ...... 56
13.1
Termination Materials ........................................ 56
13.2
Marking .............................................................. 56
13.3
Carrier Package Format ..................................... 56
13.4
Resistance to Soldering ..................................... 56
14 IPC-7358 AREA ARRAY COMPONENTS
(BGA, FBGA, CGA)
.............................................. 57
14.1
Area Array Configurations ................................ 57
14.1.1
BGA Packages ................................................... 57
14.1.2
Fine Pitch BGA Package (FBGA) .................... 58
14.1.3
Ceramic Column Grid Arrays (CGA) ............... 58
14.2
General Configuration Issues ............................ 59
14.2.1
Device Outlines ................................................. 59
14.2.2
Contact Matrix Options ..................................... 59
14.2.3
Selective Depopulation ...................................... 60
14.2.4
Attachment Site Planning .................................. 60
14.2.5
Defining Contact Assignment ............................ 61
14.3
Handling and Shipping ...................................... 61
14.4
Land Pattern Analysis ........................................ 61
14.4.1
Land Approximation .......................................... 61
14.4.2
Total Variation .................................................... 61
14.4.3
Future Ball Conditions ...................................... 62
14.4.4
Land Pattern Calculator ..................................... 62
15 IPC-7359 NO LEAD COMPONENTS (QFN,
SON, LCC)
............................................................ 62
15.1
LCC .................................................................... 62
15.1.1
Marking .............................................................. 63
15.1.2
Carrier Package Format ..................................... 63
15.1.3
Process Considerations ...................................... 63
15.2
Quad Flat No-Lead (QFN) ................................ 63
15.2.1
Marking .............................................................. 64
15.2.2
Carrier Package Format ..................................... 64
15.2.3
Process Considerations ...................................... 64
15.2.4
Solder Resist Considerations ............................. 64
15.3
Small Outline No-Lead (SON) ......................... 64
15.3.1
Marking .............................................................. 64
15.3.2
Carrier Package Format ..................................... 65
15.3.3
Process Considerations ...................................... 65
15.3.4
Solder Resist Considerations ............................. 65
16 ZERO COMPONENT ORIENTATIONS ................ 65
APPENDIX A (Informative) Test Patterns –
Process Evaluations
......................... 71
APPENDIX B (Informative) Abbreviations
and Definitions
.................................. 73
APPENDIX C IPC-7351 Land Pattern Viewer ......... 74
Figures
Figure 3-1
Profile Tolerancing Method ............................... 6
Figure 3-2 Example of 3216 (1206) Capacitor
Dimensioning for Optimum Solder Fillet
Condition ........................................................... 7
Figure 3-3 Profile Dimensioning of Gull-Wing
Leaded SOIC .................................................... 8
Figure 3-4
Pitch for Multiple Leaded Components .......... 11
Figure 3-5
Courtyard Boundary Area Condition .............. 15
Figure 3-6 Component Orientation for Wave-Solder
Applications .................................................... 21
Figure 3-7
Alignment of Similar Components .................. 21
Figure 3-8
Panel/Local Fiducials ...................................... 22
Figure 3-9
Local Fiducials ................................................ 23
Figure 3-10
Fiducial Locations on a Printed Board ........... 23
Figure 3-11
Fiducial Size and Clearance Requirements ... 24
IPC-7351 February 2005
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Figure 3-12 Use of Vias in High Component Density
Printed Circuit Boards .................................... 25
Figure 3-13 Conductor Routing Capability Test Pattern .... 25
Figure 3-14 Land Pattern to Via Relationship .................... 26
Figure 3-15 Examples of Via Positioning Concepts .......... 26
Figure 3-16 Vias Under Components ................................ 27
Figure 3-17 Conductor Description .................................... 28
Figure 3-18 Examples of Modified Landscapes ................ 28
Figure 3-19 Typical Copper Glass Laminate Panel ........... 29
Figure 3-20 Conductor Clearance for V-Groove Scoring .. 30
Figure 3-21 Breakaway (Routed Pattern) with
Routed Slots ................................................... 31
Figure 3-22 Gang Solder Mask Window ............................ 31
Figure 3-23 Pocket Solder Mask Window ......................... 31
Figure 4-1 Component Operating Temperature Limits .... 32
Figure 5-1 Test Via Grid Concepts ................................... 34
Figure 5-2 General Relationship Between Test
Contact Size and Test Probe Misses ............. 35
Figure 5-3 Test Probe Feature Distance from
Component ..................................................... 36
Figure 7-1 Typical Process Flow for Full Surface
Mount Type 1b and 2b Surface Mount
Technology ...................................................... 40
Figure 7-2 Assembly Process Flow for Two-Side
Surface Mount with PIH ................................. 41
Figure 8-1 Packaging of Discrete Components ............... 44
Figure 8-2 Chip Resistor Construction ............................. 45
Figure 8-3 Chip Capacitor Construction .......................... 46
Figure 8-4 Inductor Construction ..................................... 46
Figure 8-5 Tantalum Capacitor Construction ................... 46
Figure 8-6 Metal Electrode Face Component
Construction .................................................... 47
Figure 8-7 Break-Away Diagram of MELF
Components ................................................... 47
Figure 8-8 SOT 23 Construction ...................................... 47
Figure 8-9 SOT 89 Construction ...................................... 48
Figure 8-10 SOD 123 Construction ................................... 48
Figure 8-11 SOT143 Construction ..................................... 48
Figure 8-12 SOT 223 Construction .................................... 49
Figure 8-13 TO252 (DPAK Type) Construction ................. 49
Figure 9-1 SOIC Construction .......................................... 50
Figure 9-2 SOP8/SOP63 Construction ............................ 50
Figure 9-3 SOP127 Construction ..................................... 51
Figure 9-4 TSSOP Construction ...................................... 51
Figure 9-5 CFP127 Construction ..................................... 51
Figure 10-1 SOJ Construction ........................................... 52
Figure 11-1 BQFP Construction ......................................... 53
Figure 11-2 SQFP and QFP Construction ......................... 53
Figure 11-3 QFPR Construction ........................................ 54
Figure 11-4 CQFP Construction ......................................... 54
Figure 12-1 PLCC Construction ......................................... 55
Figure 12-2 PLCCR Construction ...................................... 56
Figure 13-1
DIP Construction ............................................ 56
Figure 14-1
Ball Grid Array (BGA) IC Package Example .. 57
Figure 14-2 Example of Plastic BGA Package
Configurations ................................................. 57
Figure 14-3 Ceramic Column Grid Array (CGA)
Package (Cross-Sectional View) .................... 58
Figure 14-4
Bottom View of BGA Devices ......................... 59
Figure 14-5
One Package Size, Two Full Matrices ........... 59
Figure 14-6 Perimeter and Thermally Enhanced
Matrices .......................................................... 60
Figure 14-7
Staggered Matrix ............................................ 60
Figure 14-8
Selective Depopulation ................................... 60
Figure 14-9
Device Orientation and Contact A1 Position .. 61
Figure 15-1
Quad Flat No-Lead (QFN) Construction ........ 63
Figure 15-2 Quad Flat No-Lead (QFN) Construction
(Cross-Sectional View) ................................... 64
Figure 15-3
Small Outline No-Lead (SON) Construction .. 64
Figure 16-1 Zero Component Rotations for Common
Package Outlines ........................................... 66
Figure A-1 General Description of Process Validation
Contact Pattern and Interconnect .................. 71
Figure A-2 Photoimage of IPC-A-49 Test Board for
Primary Side ................................................... 72
Tables
Table 3-1 Tolerance Analysis Elements for Chip
Devices .............................................................. 11
Table 3-2 Flat Ribbon L and Gull-Wing Leads
(greater than 0.625 mm pitch) (unit: mm) ......... 12
Table 3-3 Flat Ribbon L and Gull-Wing Leads (less
than or equal to 0.625 mm pitch) (unit: mm) .... 12
Table 3-4
J Leads (unit: mm) ............................................ 13
Table 3-5 Rectangular or Square-End Components
(Capacitors and Resistors) Equal to or Larger
than 1608 (0603) (unit: mm) ............................. 13
Table 3-6 Rectangular or Square-End Components
(Capacitors and Resistors) Smaller than
1608 (0603) (unit: mm) ..................................... 13
Table 3-7 Cylindrical End Cap Terminations (MELF)
(unit: mm) .......................................................... 13
Table 3-8
Bottom Only Terminations (unit: mm) ............... 13
Table 3-9 Leadless Chip Carrier with Castellated
Terminations (unit: mm) .................................... 13
Table 3-10
Butt Joints (unit: mm) ........................................ 14
Table 3-11 Inward Flat Ribbon L and Gull-Wing Leads
(Tantalum Capacitors) (unit: mm) ..................... 14
Table 3-12
Flat Lug Leads (unit: mm) ................................. 14
Table 3-13
Flat, No Lead (unit: mm) ................................... 14
Table 3-14
Small Outline (SO), No-Lead (unit: mm) .......... 14
Table 3-15
IPC-7351 Land Pattern Naming Convention .... 16
Table 3-16 Product Categories and Worst-Case
Use Environments for Surface Mounted
Electronics (For Reference Only) ..................... 19
February 2005 IPC-7351
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Table 3-17 Conductor Width Tolerances, 0.046 mm
[0.00181 in] Copper, mm [in] ............................ 28
Table 3-18 Feature Location Accuracy (units: mm [in]) ...... 28
Table 6-1 Printed Board Structure Comparison ................ 37
Table 6-2 PCB Structure Selection Considerations .......... 38
Table 6-3 PCB Structure Material Properties .................... 38
Table 14-1 JEDEC Standard JEP95 Allowable Ball
Diameter Variations for FBGA (mm) ................. 58
Table 14-2 Ball Diameter Sizes (mm) ................................. 61
Table 14-3 Land Approximation (mm) ................................. 62
Table 14-4 BGA Variation Attributes (mm) .......................... 62
Table 14-5 Land-to-Ball Calculations for Current and
Future BGA Packages (mm) ............................. 62
IPC-7351 February 2005
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