IPC-7351-2005_表面贴装焊盘布局设计和标准通用要求.pdf - 第28页

ｗｗｗ．ｂｚｆｘｗ．ｃｏｍ 3.2 Design Producibility As part of the planning cycle of a product’ s development, a concurrent engineering task group should be assembled to determine the criteria for each new design. During this plannin…

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COMPONENT, CATEGORY LAND PATTERN NAME

Thin Quad Flat Packages, 0.50 mm Pitch, Height ≤ 1.60 mm ........ TSQFP50P + Lead Span L1 X Lead Span L2 Nominal - Pin Qty

Thin Quad Flat Packages, 0.40 mm Pitch, Height ≤ 1.60 mm ........ TSQFP40P + Lead Span L1 X Lead Span L2 Nominal - Pin Qty

Thin Quad Flat Packages, 0.30 mm Pitch, Height ≤ 1.60 mm ........ TSQFP30P + Lead Span L1 X Lead Span L2 Nominal - Pin Qty

Ceramic Quad Flat Packages, 1.27 mm Pitch ................................. CQFP127P + Lead Span L1 X Lead Span L2 Nominal - Pin Qty

Ceramic Quad Flat Packages, 0.80 mm Pitch ................................... CQFP80P + Lead Span L1 X Lead Span L2 Nominal - Pin Qty

Ceramic Quad Flat Packages, 0.635 mm Pitch ................................. CQFP63P + Lead Span L1 X Lead Span L2 Nominal - Pin Qty

Quad Flat No Lead Packages 0.80 mm Pitch ................... QFN80P - Body Width X Body Length in Metric - Pin Qty + Thermal Pad

Quad Flat No Lead Packages 0.65 mm Pitch ................... QFN65P - Body Width X Body Length in Metric - Pin Qty + Thermal Pad

Quad Flat No Lead Packages 0.50 mm Pitch ................... QFN50P - Body Width X Body Length in Metric - Pin Qty + Thermal Pad

Quad Flat No Lead Packages 0.40 mm Pitch ................... QFN40P - Body Width X Body Length in Metric - Pin Qty + Thermal Pad

Quad Leadless Ceramic Chip Carriers (JEDEC Standard Package) .............. LCC + Body Width X Body Length in Metric - Pin Qty

Quad Leadless Ceramic Chip Carriers (Pin 1 on Side) ................................. LCCS + Body Width X Body Length in Metric - Pin Qty

Quad Bottom Chip Carrier (JEDEC MO-217B) ............................................. QBCC + Body Width X Body Length in Metric - Pin Qty

Resistors, Chip ......................................................................................................................................... RESC + Body Size in Metric

Resistors, Chip, Array .................................................................. RESCA + Pitch P + Body Width X Body Length in Metric - Pin Qty

Resistors, Molded ..................................................................................................................................... RESM + Body Size in Metric

Resistors, MELF ................................................................................................................................ RESMELF + Body Size in Metric

Small Outline IC, J-Leaded 300, 350, 400, 450 mil Body Width (Pitch 1.27 mm) ............. SOJ127P + Lead Span Nominal - Pin Qty

Small Outline IC, J-Leaded (Pitch 0.65 mm) ........................................................................ SOJ65P + Lead Span Nominal - Pin Qty

Small Outline Integrated Circuit, 1.27 mm Pitch (Standard 50 mil Pitch SOICs) ............. SOIC127P + Lead Span Nominal - Pin Qty

Small Outline Packages, 1.27 mm Pitch (Nonstandard 50 mil Pitch SOICs) .................... SOP127P + Lead Span Nominal - Pin Qty

Small Outline Packages, 1.00 mm Pitch ............................................................................ SOP100P + Lead Span Nominal - Pin Qty

Small Outline Packages, 0.80 mm Pitch .............................................................................. SOP80P + Lead Span Nominal - Pin Qty

Small Outline Packages, 0.65 mm Pitch .............................................................................. SOP65P + Lead Span Nominal - Pin Qty

Small Outline Packages, 0.635 mm Pitch ............................................................................... SOP63 + Lead Span Nominal - Pin Qty

Shrink Small Outline Packages, 0.50 mm Pitch ................................................................ SSOP50P + Lead Span Nominal - Pin Qty

Shrink Small Outline Packages, 0.40 mm Pitch ................................................................ SSOP40P + Lead Span Nominal - Pin Qty

Shrink Small Outline Packages, 0.30 mm Pitch ................................................................ SSOP30P + Lead Span Nominal - Pin Qty

Thin Small Outline Packages, Height is ≤ 1.60 mm, 1.27 mm Pitch ............................... TSOP127P + Lead Span Nominal - Pin Qty

Thin Small Outline Packages, Height is ≤ 1.60 mm, 1.00 mm Pitch ............................... TSOP100P + Lead Span Nominal - Pin Qty

Thin Small Outline Packages, Height is ≤ 1.60 mm, 0.80 mm Pitch ..................................TSOP80P + Lead Span Nominal - Pin Qty

Thin Small Outline Packages, Height is ≤ 1.60 mm, 0.65 mm Pitch ................................. TSOP65P + Lead Span Nominal - Pin Qty

Thin Shrink Small Outline Packages, Height is ≤ 1.60 mm, 0.55 mm Pitch ................... TSSOP55P + Lead Span Nominal - Pin Qty

Thin Shrink Small Outline Packages, Height is ≤ 1.60 mm, 0.50 mm Pitch ................... TSSOP50P + Lead Span Nominal - Pin Qty

Thin Shrink Small Outline Packages, Height is ≤ 1.60 mm, 0.40 mm Pitch ................... TSSOP40P + Lead Span Nominal - Pin Qty

Thin Shrink Small Outline Packages, Thin (Height is ≤ 1.60 mm) 0.30 mm Pitch .......... TSSOP30P + Lead Span Nominal - Pin Qty

Very Small Outline Packages, 0.762 mm Pitch (0.30 in Pitch) ........................................ VSOP762P + Lead Span Nominal - Pin Qty

SOD (Example: SOD3705 = SOD123) ................................................................................ SOD + Lead Span Nominal + Body Width

SON - Dual No Lead Packages 0.3 - 0.8 mm Pitch .................... SON + Pitch (P) - Body Width X Body Length - Pin Qty + Thermal Pad

SOT89 (JEDEC Standard Package) .......................................................................................................................................... SOT89

SOT143 (JEDEC Standard Package) ...................................................................................................................................... SOT143

SOT343 (JEDEC Standard Package) ...................................................................................................................................... SOT343

SOT143 Reverse (JEDEC Standard Package) ..................................................................................................................... SOT143R

SOT343 Reverse (JEDEC Standard Package) ..................................................................................................................... SOT343R

SOT223 (JEDEC Standard Package) (Example: SOT230P700-4N) ........................ SOT + Pitch (P) + Lead Span Nominal - Pin Qty

SOT Generic Package 0.65 mm Pitch .................................................................................. SOT65P + Lead Span Nominal - Pin Qty

SOT Generic Package 0.95 mm Pitch .................................................................................. SOT95P + Lead Span Nominal - Pin Qty

TO (Generic DPAK) (Example: TO228P970-3N) ...................................................................... TO + Pitch (P) + Lead Span + Pin Qty

February 2005 IPC-7351

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3.2 Design Producibility As part of the planning cycle of

a product’s development, a concurrent engineering task

group should be assembled to determine the criteria for

each new design. During this planning phase, the product

function and conﬁguration is clearly deﬁned and the assem-

bly process options outlined. Product size, component

types, projected volume and the level of manufacturing

equipment available may affect process options.

Following the substrate development, the assembly will be

evaluated for many of the fundamentals necessary to insure

a successful SMT process. Speciﬁc areas addressed during

the evaluation include:

a) Land pattern concepts

b) Component selection

c) Mounting substrate design

d) Assembly methods

e) Method of test

f) Phototool generation

g) Meeting minimum solder joint requirements

h) Stencil ﬁxture requirements

i) Wave solder ﬁxture requirements

j) Providing access for inspection

k) Providing access for rework and repair

3.2.1 SMT Land Pattern The use of process proven land

patterns for the solder attachment of surface mount devices

will provide a benchmark to evaluate solder joint quality.

Land pattern geometry and spacing utilized for each com-

ponent type must accommodate all physical variables

including size, material, lead contact design and plating.

3.2.2 Standard Component Selection Whenever pos-

sible, SMT devices should be selected from standard con-

ﬁgurations. The standard components will be available

from multiple sources and will usually be compatible with

assembly processes. For those devices developed to meet

speciﬁc applications, standard packaging is often available.

Select a package type that will be similar in materials and

plating of standard device types when possible.

3.2.3 Circuit Substrate Development Design the circuit

substrate to minimize excessive costs. High-density surface

mount technology often pushes the leading edge of sub-

strate technology. When estimating circuit density, allow

for the greatest latitude in fabrication processes and toler-

ance variables. Before adopting extreme ﬁne-line and uti-

lizing small plated holes, understand the cost impact, yield,

and long-term reliability of the product.

3.2.4 Assembly Considerations Manufacturing effi-

ciency includes component placement. Within the con-

straints of circuit function, maintaining a consistent spacing

between components and common orientation or direction

of polarized devices can have an impact on all steps of the

assembly process. In addition, when common orientation is

maintained, machine programming is simpliﬁed and com-

ponent veriﬁcation, solder inspection and repair are simpli-

ﬁed (See Figures 3-9 and 3-18).

3.2.5 Provision for Automated Test Testability of the

assembled circuit substrate must be planned well in

advance. If component level In-Circuit Test (ICT) is neces-

sary, one test probe contact area is required for each com-

mon node or net. Ideally, all probe contact lands are on one

side, typically the secondary side (double sided test ﬁxtures

are signiﬁcantly more expensive). Functional testing may

also employ the same test nodes used for in-circuit test but

will include all connectors that interface to cables and other

assemblies.

3.2.6 Documentation for SMT Documentation used to

fabricate the circuit substrate and assemble the product

must be accurate and easy to understand. Details, speciﬁ-

cations and notes will guide both the assembly processing

and control the quality level of a product. Unique materials

or special assembly instructions, such as moisture sensitiv-

ity and handling, should be included on the face of the

detail drawings or in the documentation package.

3.3 Environmental Constraints

3.3.1 Moisture Sensitive Components

Plastic encapsu-

lated IC packages may be susceptible to absorbing mois-

ture. The component manufacturer usually provides spe-

cialized packaging for these, and furnish instructions for

use or maintaining those parts in a controlled storage envi-

ronment. IPC/JEDEC J-STD-033 provides proper handling

and testing methods such as for moisture sensitivity.

3.3.2 End-Use Environment Considerations Com-

pounds, materials and assembly processes should consider

the products end-use environment. Table 3-16 provides

information on the end-use environment characteristics for

nine basic environments.

IPC-7351 February 2005

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Table 3-16 Product Categories and Worst-Case Use Environments for Surface Mounted Electronics (For Reference Only)

Product Category

(Typical Application)

Temperature, °C / °F

(1)

Worst-Case Use Environment

Storage Operation

Tmin

(2)

°C/°F

Tmax

(2)

°C/°F

∆T

(3)

°C/°F

(4)

hrs Cycles/year

Typical years

of Service

Approx. Accept.

Failure Risk, %

Consumer -40/85 0/55 0/32 60/140 35/63 12 365 1-3 1

Computers and Peripherals -40/85 0/55 0/32 60/140 20/36 2 1460 5 0.1

Telecomm -40/85 -40/85 -40/-40 85/185 35/63 12 365 7-20 0.01

Commercial Aircraft -40/85 -40/85 -55/-67 95/203 20/36 12 365 20 0.001

Industrial and Automotive -

Passenger Compartment

-55/150 -40/85 -55/-67 95/203 20/36

&40/72

&60/108

&80/144

185

100

10-15 0.1

Military

(ground and shipboard)

-40/85 -40/85 -55/-67 95/203 40/72

&60/108

100

265

10-20 0.1

Space

leo

geo

-40/85 -40/85

-55/-67 95/203

3/5.4

to 100/180

8760

365

5-30 0.001

Military Aircraft

Maintenance

-55/125 -40/85

-55/-67 125/257 40/72

60/108

80/144

100

10-20 0.01

&20/36 1 120

Automotive

(under hood)

-55/150 -40/125 -55/-67 125/257 60/108

&100/180

&140/252

1000

300

10-15 0.1

& = in addition

1. All categories may be exposed to a process temperature range of 18°C to 260°C [64.4°F to 500°F].

2. Tmin and Tmax are the operational (test) minimum and maximum temperatures, respectively, and do not determine the maximum ∆T.

3. ∆T represents the maximum temperature swing, but does not include power dissipation effects; for power dissipation calculate ∆T; power dissipation can make pure temperature cycling accelerated testing

signiﬁcantly inaccurate. It should be noted that the temperature range, ∆T, is not the difference between Tmin and Tmax ; ∆T is typically signiﬁcantly less.

4. The dwell time, t

, is the time available for the creep of the solder joints during each temperature half-cycle.

February 2005 IPC-7351