IPC-7351-2005_表面贴装焊盘布局设计和标准通用要求.pdf - 第73页

Leadless T ype A is intended for lid-down mounting in a socket, which places the primary heat-dissipating surface away from the mounting surface for more ef fective cooling in air-cooled systems. T ype C is a ceramic pac…

result in a worst case analysis, however as with other land

patterns in the standard, a statistical average is determined

by using the RMS (root, mean, square) value. Table 14-4

shows the total variation in the system for each of the four

ball sizes identiﬁed in the standard.

It should be noted that the target value for lands on the

substrate of the component or the board should be at Maxi-

mum Material Condition. The variation from the Maximum

Material Condition indicates that ball-to-land misalignment

is achieved by taking the maximum land size and subtract-

ing the variation. The resulting dimension would indicate

the amount of attachment area that would result from a

system where all conditions are at a negative instance. For

lands that are solder mask-deﬁned, the land size should be

increased by the amount of encroachment of the solder

mask. As an example, if the requirement is that solder

mask should be on the land by 0.05 mm, then the maxi-

mum land size should be increased by 0.1 mm. It should be

noted that for solder mask-deﬁned lands, since the land size

increases, the opportunity to route conductors between

lands is impacted by reducing the available area for con-

ductor width and spacing.

14.4.3 Future Ball Conditions Although not required for

the BGAs shown in the present release of IPC-7351, pro-

jected future ball sizes of 0.40 mm pitch and below are

shown in Table 14-2. Their projected land size approxima-

tions for ball diameters of 0.25 mm and below are shown

in Table 14-3.

14.4.4 Land Pattern Calculator The land pattern calcu-

lations for BGAs are based on ball size. As a result of ball

variation and component conditions, Table 14-5 shows the

land pattern calculator headings needed to describe the

variations in the system. This data is usually described at

the Maximum Material Condition for nonsolder mask-

deﬁned lands and is dimension ‘‘X’’ in the IPC-7351

datasheets for BGA land patterns.

15 IPC-7359 NO LEAD COMPONENTS (QFN, SON, LCC)

15.1 LCC

A leadless chip carrier is a ceramic package

with integral surface-metallized terminations. Leadless

Types A, B, and D chip carriers have a chamfered index

corner that is larger than that of Type C. Another difference

between the A, B, and D types and Type C is the feature in

the other three corners. The types A, B, and D, were

designed for socket applications and printed wiring inter-

connections. The Type C is primarily intended for direct

attachment through reﬂow soldering. This application dif-

ference is the main reason for their mechanical differences.

These packages mount in different orientations, depending

on type, mounting structure and preferred thermal orienta-

tion.

Table 14-3 Land Approximation (mm)

Nominal Ball

Diameter Reduction

Nominal

Land

Diameter

Land

Variation

0.75 25% 0.55 0.60 - 0.50

0.60 25% 0.45 0.50 - 0.40

0.50 20% 0.40 0.45 - 0.35

0.45 20% 0.35 0.40 - 0.30

0.40 20% 0.30 0.35 - 0.25

0.30 20% 0.25 0.25 - 0.20

0.25 20% 0.20 0.20 - 0.17

0.20 20% 0.15 0.15 - 0.12

0.15 20% 0.10 0.10 - 0.08

Table 14-4 BGA Variation Attributes (mm)

Nominal

Ball Size

Positional

Allowance

Ball

Tolerance

Substrate

Tolerance

Variation

RMS

Value

0.75 0.1 dia. DTP 0.25 0.10 0.25

0.60 0.1 dia. DTP 0.20 0.10 0.24

0.50 0.1 dia. DTP 0.10 0.10 0.17

0.45 0.1 dia. DTP 0.10 0.10 0.17

Table 14-5 Land-to-Ball Calculations for Current and Future BGA Packages (mm)

Land Size

Location

Allowance

Ball

Variation

PCB

Fabrication

Allowance

Ball Size

Reduction

from

Nominal

Variation

AllowanceMMC LMC Nominal MMC LMC

0.60 0.50 0.10 0.25 0.10 0.75 0.90 0.65 25% 0.25

0.50 0.40 0.10 0.20 0.10 0.60 0.70 0.50 25% 0.20

0.45 0.35 0.10 0.10 0.10 0.50 0.55 0.45 20% 0.17

0.40 0.30 0.10 0.10 0.10 0.45 0.50 0.40 20% 0.17

0.35 0.25 0.10 0.10 0.10 0.40 0.45 0.35 20% 0.17

0.25 0.20 0.05 0.10 0.05 0.30 0.35 0.25 20% 0.15

0.20 0.17 0.05 0.06 0.03 0.25 0.28 0.22 20% 0.08

0.15 0.12 0.05 0.04 0.03 0.20 0.22 0.18 20% 0.07

0.10 0.08 0.05 0.04 0.02 0.17 0.17 0.13 20% 0.07

IPC-7351 February 2005

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Leadless Type A is intended for lid-down mounting in a

socket, which places the primary heat-dissipating surface

away from the mounting surface for more effective cooling

in air-cooled systems.

Type C is a ceramic package similar to leadless Type B

except for corner conﬁguration. The 1.27 mm center fam-

ily, which includes both leadless and leaded devices, is

designed to mount on a common mounting pattern. They

may be directly attached to the mounting structure, or can

be plugged into sockets. One basic restriction is that there

shall be no terminals in the corners of the package. There

are a number of common sizes.

End terminations should be solder coated with a tin/lead

alloy or a lead free equivalent. The solder should contain

between 58 to 68% tin. Solder may be applied to the ter-

mination by hot dipping or by plating from solution. Plated

solder terminations should be subjected to a postplating

reﬂow operation to fuse the solder. The tin/lead ﬁnish

should be at least 0.0075 mm [0.0003 in] thick.

The termination shall be symmetrical, and shall not have

nodules lumps, protrusions, etc., that compromise the sym-

metry or dimensional tolerances of the part. The end termi-

nation shall cover the ends of the components, and shall

extend out to the top and bottom of the component.

Solder ﬁnish applied over precious metal electrodes shall

have a diffusion-barrier layer between the electrode metal-

lization and the solder ﬁnish. The barrier layer should be

nickel or an equivalent diffusion barrier, and should be at

least 0.00125 mm [0.00005 in] thick.

For lead free ﬁnishes a combination of tin, silver and cop-

per is the prevalent replacement for the tin/lead ﬁnish. Sol-

derability testing should be applied per IPC/EIA-J-STD-

001 to determine attachment capability of the applicable

component type.

15.1.1 Marking All parts shall be marked with a part

number and ‘‘Pin 1’’ location. ‘‘Pin 1’’ location may be

molded into the plastic body.

15.1.2 Carrier Package Format Tube carriers are pre-

ferred for best handling.

15.1.3 Process Considerations LCCs are usually pro-

cessed using standard solder reﬂow processes. Parts should

be capable of withstanding ten cycles through a standard

reﬂow system operating at 215° C [419 °F]. Each cycle

shall consist of 60 seconds exposure at 215° C [419 °F].

See IPC/JEDEC J-STD-020 for appropriate reﬂow cycles

and proﬁles when using lead free solders.

15.2 Quad Flat No-Lead (QFN) The Quad Flat No-Lead

(QFN) package is a near CSP plastic encapsulated package

with a copper leadframe substrate. This is a leadless pack-

age where electrical contact to the PCB is made by solder-

ing the lands on the bottom surface of the package to the

PCB, instead of the conventional formed perimeter leads.

The exposed die attach paddle on the bottom efficiently

conducts heat to the PCB and provides a stable ground

through down bonds or electrical connections through con-

ductive die attach material. The design of the QFN pack-

age also allows for ﬂexibility. Its enhanced electrical per-

formance enables the standard 2 GHz frequency to be

increased up to 10 GHz with some design considerations

(see Figures 15-1 and 15-2).

Solderable areas of the mating surfaces on the end termi-

nations (package bottom side) should be solder coated with

a tin/lead alloy or a lead free equivalent. Ends/sides of the

terminals are not designed as a solderable surface and are

not required to be plated, as this is a physical impossibility

with many current manufacturing processes. Solder may be

applied to the termination by hot dipping or by plating

from solution. Plated solder terminations should be sub-

jected to a postplating reﬂow operation to fuse the solder.

The tin/lead ﬁnish should be at least 0.0075 mm [0.0003

in] thick.

The termination shall be symmetrical, and shall not have

nodules lumps, protrusions, etc., that compromise the sym-

metry or dimensional tolerances of the part. The end termi-

nation shall cover the ends of the components, and shall

extend out to the top and bottom of the component.

Solder ﬁnish applied over precious metal electrodes shall

have a diffusion-barrier layer between the electrode metal-

lization and the solder ﬁnish. The barrier layer should be

nickel or an equivalent diffusion barrier, and should be at

least 0.00125 mm [0.00005 in] thick.

For lead free ﬁnishes a combination of tin, silver and cop-

per is the prevalent replacement for the tin/lead ﬁnish. Sol-

derability testing should be applied per IPC-J-STD-002 to

determine attachment capability of the applicable compo-

nent type.

IPC-7351-15-01

Figure 15-1 Quad Flat No-Lead (QFN) Construction

February 2005 IPC-7351

15.2.1 Marking All parts shall be marked with a part

number and ‘‘Pin 1’’ location. ‘‘Pin 1’’ location may be

molded into the plastic body or a chamfer/radius in the

bottom exposed pad (bottom paddle).

15.2.2 Carrier Package Format The carrier package for-

mat for QFN packages include embossed tape and reel as

well as packaging trays.

15.2.3 Process Considerations Because of the small

lead surface area and the sole reliance on printed solder

paste on the PCB surface, the formation of reliable solder

joints for the QFN package can be a challenge. This is fur-

ther complicated by the large thermal pad underneath the

package and its proximity to the inner edges of the leads.

Special considerations are needed in stencil design and

paste printing for both perimeter and thermal pads. Since

surface mount process varies from company to company,

careful process development is recommended.

The optimum and reliable solder joints on the perimeter

pads should have about 50 µm to 75 µm standoff height. A

side ﬁllet is not required since the sides are not designed as

a solderable surface (see IPC-A-610).

15.2.4 Solder Resist Considerations The solder resist

opening should be 120 µm to 150 µm larger than the land

size resulting in 60 µm to 75 µm clearance between the

copper land and solder resist. This allows for solder resist

registration tolerances, which are typically between 50 µm

to 65 µm, depending upon the board fabricators’ capabili-

ties. Typically each land on the PCB should have its own

solder resist opening with a web of solder resist between

two adjacent lands. Since the web has to be at least 75 µm

in width for the solder resist to adhere to the PCB surface,

each land can have its own solder resist opening for lead

pitch of 0.5 mm or higher, based on the land width dimen-

sions. However, for 0.4 mm pitch parts with PCB land

width of 0.25 mm, not enough space is available for solder

resist web in between the land. In such cases, it is recom-

mended to use the ‘‘gang’’ type solder resist opening

shown in Figure 3-22 where a big opening is designed

around all land on each side of the package with no solder

resist in between the land.

15.3 Small Outline No-Lead (SON) The Small Outline

No-lead Package (SON) is a rectangular semiconductor

package with metal terminals along two sides of the bottom

of the package. The terminals are either ﬂush with the bot-

tom or protruding slightly below the bottom of the pack-

age, with plastic mold compound present on three sides of

each contact. The main body of the component is generally

a molded plastic. The SON package is similar to the leaded

SOIC family, though consuming less of the PCB area in

comparison with the leaded SOIC. The part is a ‘‘lead-

less’’ package design with bottom paddle which can be

soldered to the PCB. See Figure 15-3 for an example of a

SON component.

15.3.1 Marking All parts shall be marked with a part

number and ‘‘Pin 1’’ location. ‘‘Pin 1’’ location may be

molded into the plastic body or a chamfer/radius in the

bottom exposed pad (bottom paddle).

IPC-7351-15-02

Figure 15-2 Quad Flat No-Lead (QFN) Construction (Cross-Sectional View)

IPC-7351-15-03

Figure 15-3 Small Outline No-Lead (SON) Construction

IPC-7351 February 2005

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