IPC-7351-2005_表面贴装焊盘布局设计和标准通用要求.pdf - 第42页

5 TESTABILITY 5.1 Board and Assembly Test There are five basic types of tests which can be performed on SMT boards. These are: a) Bare-board test which checks the unpopulated board for shorts and opens b) Manufacturing de…

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completely cover the conductor. A more precise registration
is necessary because of the tight tolerance needed to cover
the conductors without encroaching on the land area. PCB
manufacturers are required to keep the soldermask material
off the land. Clearance conditions can vary from 0.0 mm
[0.0 in] to 0.1 mm [0.0040 in].
3.5.3 Land Pattern Surface Finishes The soldermask
openings expose the land patterns for attachment of surface
mount components. These are usually copper-based and
therefore need protection in order to prevent the copper
from oxidizing, thus resulting in poor solderability of the
surface land patterns. The protection of the land patterns
may be accomplished by organic solderability protective
(OSP) coatings or metallic finishes such as solder coating,
gold, silver, or palladium platings.
The choice of coatings or plating is dependent on the
assembler’s preference or the type of components being
assembled. A single coating or plating finish is preferred
for the entire board. Mixing the surface finish types is not
recommended due to the different process steps required.
Selective finishes may be necessary based on the mix of
component types, lead pitch and attachment process or lead
termination finish characteristics.
4 COMPONENT QUALITY VALIDATION
4.1 Validation Techniques
Because of the variety of
component tolerances, and the possibility that tolerances
may vary on components, users are encouraged to establish
validation of the land pattern and component geometry. In
addition, components should be selected and qualified to
meet the end products maximum operating temperature
limits. Figure 4-1 shows a chart referencing the upper and
lower limits of various components.
Validations of parts and circuits may be accomplished
through the use of standard test patterns. These patterns
may be used not only to evaluate a particular part to a land
pattern, but may also be used to evaluate component prod-
ucts’ capability to stand up to various processes being used
in assembling surface mounted parts.
IPC-7351-3-21
Figure 3-21 Breakaway (Routed Pattern) with Routed Slots
IPC-7351-3-22
Figure 3-22 Gang Solder Mask Window
Solder Mask
Land
Gang
▼
▼
▼
C
L
IPC-7351-3-23
Figure 3-23 Pocket Solder Mask Window
Land
Conductor
▼
C
L
Pocket
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5 TESTABILITY
5.1 Board and Assembly Test
There are five basic types
of tests which can be performed on SMT boards. These
are:
a) Bare-board test which checks the unpopulated board for
shorts and opens
b) Manufacturing defect analysis which checks the popu-
lated board for soldering shorts
c) In-circuit test operational verification of each individual
component
d) Functional test operational verification of functional
block of circuits
e) Combinational test limited integration of in-circuit and
functional test
The first test type is a bare-board test performed by the
board fabricator. The remaining four test types are loaded
on assembled board tests and performed after assembly.
The bare-board test should be mandatory, while the loaded
board may be tested using any one or a combination of the
four loaded board tests.
5.1.1 Bare-Board Test In testing printed boards using
through-hole technology, the defect rate and the test meth-
ods chosen are the principle determiners of overall test
cost. Real-estate considerations (specifically the percentage
of nodes that are available for bed-of-nails probing) are not
a concern, since the holes provide 100% nodal access. In
testing surface mount boards, however, real-estate consid-
erations (in addition to defect rates) have an impact on test
costs, since nodal access determines which test methods
are possible and effective.
The use of design concepts with grid-based 100% nodal
access from either side of the board may be the most eco-
nomical approach from the total process perspective. If the
grid-based test land concept is used, the test fixtures for
bare and assembled board tests will not become obsolete
through later board connectivity revisions if the test nodes
are not moved. Also, if the printed board uses buried vias,
the grid-based test land concept with 100% nodal access
may provide access to buried nets from the ends of the
nets; this is a benefit realized during the bare-board test.
5.1.2 Assembled Board Test The method of test must
be determined prior to design layout. If the defect rate is
relatively high, most boards will require diagnosis, and the
economics of automatic in-circuit test (ICT) will demand
that full nodal access be provided within the board layout.
If the defect rate is low, ICT may be omitted and rely on a
functional test. Extremely low defect levels would theoreti-
cally allow 0 % nodal access (no bed-of-nails test at all),
applying only a simple pass/no-pass test through a common
interface connector.
The major considerations in determining nodal access are:
• Defect rate.
• Diagnostic capability.
• Real-estate impact.
• Board area.
• Layer count.
• Cost impact.
IPC-7351-4-01
Figure 4-1 Component Operating Temperature Limits
125
85
125
120
0˚C
–40–40
–10
–55
Ceramic ICs
Plastic ICs
Capacitors
Resistors
▼ ▼
▼
▼
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Determining the percentage of nodal access to design into
a board layout requires trading off all the issues discussed
previously: defect rate, test development cost, test opera-
tion costs including manual troubleshooting costs, and, of
course, impacts on real estate. Short of having no defects
at all, full nodal access remains the most desirable option.
As with through-hole technology boards, once the board is
designed (nodal access fixed) and its tests are designed
(test methods fixed), the defect rate becomes the primary
key to reducing test costs. Therefore, defect reporting,
analysis, and correction/prevention are imperative. This
may involve closer supplier relationships to reduce compo-
nent and board level problems, and in-house action to
reduce process-induced problems.
5.2 Nodal Access In the early stages of product develop-
ment cycles, test philosophies and strategies are often
undefined. This is especially true when a company is mov-
ing from one level of packaging technology to the next
higher level of packaging technology, for example, from
through-hole technology to surface mount technology or
from fine-pitch lead-frame packaged ICs to BGA or CSP.
During these transition periods, the concurrent engineering
approach is essential for designing nodal access for test-
ability into the product. Concurrent engineering is the prin-
ciple vehicle by which test priorities can and should be
moved up to the beginning of the design cycle and
addressed with a higher priority. In the early stages of a
design, a test philosophy should be clearly defined, then a
strategy for executing the tests can be implemented. An
ideal philosophy to adopt is one that identifies all of the
different test types and the level of test that each type
requires.
5.2.1 Test Philosophy The test philosophy should be
written to encompass whatever combination of tests are
necessary for the product. Then, a simple strategy for
implementing the required tests can be defined prior to
beginning the design process. Planning testability at the
beginning of a product development cycle instead of the
end can result in significantly lower test costs per node and
provide higher nodal accessibility throughout the entire
process from initial design to final test.
The best test philosophy to adopt is one that will make
provisions for executing every test method available. Even
when the product testing procedure is well defined at the
beginning of the development cycle, it may change after
the design is complete. Some things to consider in outlin-
ing a test philosophy:
a) Strategic placement of all component vias.
b) Provide access to every node of every net.
c) Access of every node from one side of the board is pre-
ferred.
d) Correct test pad geometries and clearances.
Even in the higher density designs, the philosophy of pro-
viding 100% access to every node of every net from either
side of the board can be accomplished. However, this deci-
sion must be made at the beginning of a design.
5.2.2 Test Strategy for Bare Boards After the product
test philosophy has been established, a test strategy or pro-
cedure can be defined. For an overview of several elements
of a procedure, consider the following:
a) Vision inspection of inner layers using AOI.
b) Vision inspection of O/L land/via connections.
c) Probe only vias on either side for bare board test.
d) Do not damage SMT lands with probe tips.
e) Probe secondary side vias for loaded test board.
f) Screen paste on vias for airtight board.
The actual product test strategy must be organized by all of
the concurrent engineering team members who will be
involved in the testing process. This will ensure that the
integration of the various test types and procedures will not
have too much redundancy, or create gaps that may endan-
ger test integrity.
5.3 Full Nodal Access for Assembled Board The num-
ber of test probes needed to test the board is equal to the
total number of device nodes or common connection
between devices. However, in the case of most dense sur-
face mount designs, this often requires the use of a double-
sided, or clamshell test fixture because all of the nodes are
not accessible from one side of the board.
In-Circuit Test (ICT) only needs to have access to one node
per net. Every net has at least two nodes. Some nets have
many nodes, for example, on memory boards one net may
be connected to many nodes. In order to achieve full integ-
rity at the ICT level, access to only one node of each net is
all that is required. Therefore, the total number of test
probes required to perform the ICT is significantly less
than the number required for the bare board test.
For fine-pitch components, it is good design practice to
distribute approximately half of the test vias to the inside
of the land pattern and the other half to the outside of the
land pattern as shown in Figure 5-1. This accomplishes two
objectives:
1. The maximum density of test points established for a
given piece of test equipment is not exceeded.
2. Wider distribution of test points reduces the high-
pressure point areas which cause fixture bowing during
vacuum or mechanical actuation.
5.3.1 In-Circuit Test Accommodation Specific via lands
and holes can be reserved and accessed for automatic
in-circuit test (ICT). The via land location for each com-
mon network in a circuit is matched to a test probe contact
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