MIL- STD-883F 2004 TEST METHOD STANDARD MICROCIRCUITS.pdf - 第122页

MIL-STD-883F METHOD 1019.6 7 March 2003 6 b. The test will b e carried out in su ch a fash ion tha t the ca se of the device under t est wi ll have a temper ature wi thin the range 24°C ± 6°C. c. Wher e possi ble, t he r…

MIL-STD-883F

METHOD 1019.6

7 March 2003

3.9.3 Bias and loading conditions.

Bias conditions for test devices during irradiation or accelerated annealing shall be

within ±10 percent of those specified by the test plan. The bias applied to the test devices shall be selected to produce the

greatest radiation induced damage or the worst-case damage for the intended application, if known. While maximum

voltage is often worst case some bipolar linear device parameters (e.g. input bias current or maximum output load current)

exhibit more degradation with 0 V bias. The specified bias shall be maintained on each device in accordance with the test

plan. Bias shall be checked immediately before and after irradiation. Care shall be taken in selecting the loading such that

the rise in the junction temperature is minimized.

3.10 Post-irradiation procedure

. Unless otherwise specified, the following time intervals shall be observed:

a. The time from the end of an irradiation to the start of electrical measurements shall be a maximum of 1 hour unless

Condition D is used, in which case the maximum time shall be 72 hours.

b. The time to perform the electrical measurements and to return the device for a subsequent irradiation, if any, shall

be within two hours of the end of the prior irradiation unless Condition D is used, in which case the maximum time

shall be 120 hours.

To minimize time dependent effects, these intervals shall be as short as possible. The sequence of parameter

measurements shall be maintained constant throughout the tests series.

3.11 Extended room temperature anneal test

. The tests of 3.1 through 3.10 are known to be overly conservative for

some devices in a very low dose rate environment (e.g. dose rates characteristic of space missions). The extended room

temperature anneal test provides an estimate of the performance of a device in a very low dose rate environment even

though the testing is performed at a relatively high dose rate (e.g. 50-300 rad(Si)/s). The procedure involves irradiating the

device per steps 3.1 through 3.10 and post-irradiation subjecting the device under test to a room temperature anneal for an

appropriate period of time (see 3.11.2c) to allow leakage-related parameters that may have exceeded their pre-irradiation

specification to return to within specification. The procedure is known to lead to a higher rate of device acceptance in cases:

a. where device failure when subjected to the tests in 3.1 through 3.10 has been caused by the buildup of trapped

positive charge in relatively soft oxides, and

b. where this trapped positive charge anneals at a relatively high rate.

3.11.1 Need to perform an extended room temperature anneal test

. The following criteria shall be used to determine

whether an extended room temperature anneal test is appropriate:

a. The procedure is appropriate for either MOS or bipolar technology devices.

b. The procedure is appropriate where only parametric failures (as opposed to functional failure) occurs. The parties

to the test shall take appropriate steps to determine that the device under test is subject to only parametric failure

over the total ionizing dose testing range.

c. The procedure is appropriate where the natural annealing response of the device under test will serve to correct the

out-of-specification of any parametric response. Further, the procedure is known to lead to a higher rate of device

acceptance in cases where the expected application irradiation dose rate is sufficiently low that ambient

temperature annealing of the radiation induced trapped positive charge can lead to a significant improvement of

device behavior. Cases where the expected application dose rate is lower than the test dose rate and lower than

0.1 rad(Si)/s should be considered candidates for the application of this procedure. The parties to the test shall

take appropriate steps to determine that the technology under test can provide the required annealing response

over the total ionizing dose testing range.

3.11.2 Extended room temperature anneal test procedure

. If the device fails the irradiation and testing specified in 3.1

through 3.10, an additional room temperature annealing test may be performed as follows:

a. Following the irradiation and testing of 3.1 through 3.10, subject the device under test to a room temperature

anneal under worst-case static bias conditions. For information on worst case bias see 3.9.3,

MIL-STD-883F

METHOD 1019.6

7 March 2003

b. The test will be carried out in such a fashion that the case of the device under test will have a temperature within

the range 24°C ± 6°C.

c. Where possible, the room temperature anneal should continue for a length of time great enough to allow device

parameters that have exceeded their pre-irradiation specification to return to within specification or post-irradiation-

parametric limit (PIPL) as established by the manufacturer. However, the time of the room temperature anneal

shall not exceed t

max

, where

spec

max

spec

is the total ionizing dose specification for the part and R

max

is the maximum dose rate for the intended use.

d. Test the device under test for electrical performance as specified in 3.7 and 3.8. If the device under test passes

electrical performance tests following the extended room temperature anneal, this shall be considered acceptable

performance for a very low dose rate environment in spite of having previously failed the post-irradiation and

electrical tests of 3.1 through 3.10.

3.12 MOS accelerated annealing test

. The accelerated annealing test provides an estimate of worst-case degradation of

MOS microcircuits in low dose rate environments. The procedure involves heating the device following irradiation at

specified temperature, time and bias conditions. An accelerated annealing test (see 3.12.2) shall be performed for cases

where time dependent effects (TDE) can cause a device to degrade significantly or fail. Only standard testing shall be

performed as specified in 3.1 through 3.10 for cases where TDE are known not to cause significant device degradation or

failure (see 3.12.1) or where they do not need to be considered, as specified in 3.12.1.

3.12.1 Need to perform accelerated annealing test

. The parties to the test shall take appropriate steps to determine

whether accelerated annealing testing is required. The following criteria shall be used:

a. The tests called out in 3.12.2 shall be performed for any device or circuit type that contains MOS circuit elements

(i.e., transistors or capacitors).

b. TDE tests may be omitted if:

1. circuits are known not to contain MOS elements by design, or

2. the ionizing dose in the application, if known, is below 5 krad(Si), or

3. the lifetime of the device from the onset of the irradiation in the intended application, if known, is short

compared with TDE times, or

4. the test is carried out at the dose rate of the intended application, or

5. the device type or IC technology has been demonstrated via characterization testing not to exhibit TDE

changes in device parameters greater than experimental error (or greater than an otherwise specified upper

limit) and the variables that affect TDE response are demonstrated to be under control for the specific vendor

processes.

At a minimum, the characterization testing in (5) shall include an assessment of TDE on propagation delay,

output drive, and minimum operating voltage parameters. Continuing process control of variables affecting

TDE may be demonstrated through lot sample tests of the radiation hardness of MOS test structures.

c. This document provides no guidance on the need to perform accelerated annealing tests on technologies that do

not include MOS circuit elements.

MIL-STD-883F

METHOD 1019.6

7 March 2003

3.12.2 Accelerated annealing test procedure

. If the device passes the tests in 3.1 through 3.10 or if it passes 3.11 (if that

procedure is used) to the total ionizing dose level specified in the test plan or device specification or drawing and the

exclusions of 3.12.1 do not apply, the accelerated annealing test shall be conducted as follows:

a. Overtest

1. Irradiate each test device to an additional 0.5-times the specified dose using the standard test conditions (3.1

through 3.10). Note that no electrical testing is required at this time.

2. The additional 0.5-times irradiation in 3.12.2.a.1may be omitted if it has been demonstrated via

characterization testing that:

a. none of the circuit propagation delay, output drive, and minimum operating voltage parameters recover

toward their pre-irradiation value greater than experimental accelerated annealing test of 3.12.2.b, and

b. the irradiation biases chosen for irradiation and accelerated annealing tests are worst-case for the

response of these parameters during accelerated annealing.

The characterization testing to establish worst-case irradiation and annealing biases shall be performed at the

specified level. The testing shall at a minimum include separate exposures under static and dynamic

irradiation bias, each followed by worst-case static bias during accelerated annealing according to 3.12.2.b.

b. Accelerated annealing

. Heat each device under worst-case static bias conditions in an environmental chamber

according to one of the following conditions:

1. At 100°C ±5°C for 168 ±12 hours, or

2. At an alternate temperature and time that has been demonstrated via characterization testing to cause equal

or greater change in the parameter(s) of interest, e.g., propagation delay, output drive, and minimum

operating voltage, in each test device as that caused by 3.12.2.b.1, or

3. At an alternate temperature and time which will cause trapped hole annealing of >60% and interface state

annealing of <10% as determined via characterization testing of NMOS test transistors from the same

process. It shall be demonstrated that the radiation response of test transistors represent that of the device

under test.

c. Electrical testing.

Following the accelerated annealing, the electrical test measurements shall be performed as

specified in 3.8 and 3.9.