MIL- STD-883F 2004 TEST METHOD STANDARD MICROCIRCUITS.pdf - 第670页

MIL-STD-883F METHOD 5010.4 18 June 2004 20 APPENDIX I 10.3 Layout verif icat ion . The manufac turer shall retai n the res ults of full mask level desi gn rule c he cks, electr ical ru le checks , and c onnecti vity c he…

MIL-STD-883F

METHOD 5010.4

18 June 2004

APPENDIX I

COMPUTER AIDED DESIGN (CAD)

CERTIFICATION REQUIREMENTS

10. SCOPE.

10.1 Scope

. Additional line certification requirements. This appendix defines additional line certification requirements.

The answers to the questions in this appendix shall be provided to the qualifying activity for approval. The manufacturer

shall have the following additional information on file and available for review.

a. Design/layout rules as a manufacturer's controlled document.

b. A list of the cells in the manufacturer's cell library, cell performance data, and simulation verification data, if

applicable.

c. Process monitor design used by the manufacturer.

d. Standard evaluation circuit implementation used by the manufacturer for qualification and qualification

conformance inspection (QCI).

e. JEDEC benchmark macro set (see JEDEC standards 12, 12-1, 12-2, and 12-3), delay simulation data, if

applicable.

f. A list of the software packages (including names and current version) used by the manufacturer in the circuit

design process.

g. Design rule check (DRC) verification. DRC software shall be run on a design which contains known design rule

violations.

h. Electrical rule check (ERC) verification. ERC software shall be run on a design which contains known electrical

rule violations.

i. Layout versus schematic (LVS) checker.

j. If the manufacturer's design methodology is based on the "correct by construction" approach, distinct DRC, ERC,

and LVS software is unnecessary and may not exist. In this case, the provisions of g., h., and i. do not apply.

Instead, the manufacturer will provide suitable example data to demonstrate the correct performance of "correct

by construction" software.

10.2 Functional delay simulation

. To be retained by manufacturer; simulation to be derived from each final application

specific electrical design and layout (i.e., post-routed design). Simulation will be done using actual delays and parasitics

computed from the placement and layout of the device as it will be fabricated. Actual delays shall include the contribution

associated with the delay through the gate, as well as the contribution due to actual metal capacitance and device loading

on the output(s). Using these actual delays, the application specific integrated circuit (ASIC) designer shall insure that there

are no timing violations remaining in the circuit. Such timing violations shall include, but not be limited to, setup, hold, critical

delay path, and circuit race conditions due to variations in process, temperature and supply voltage. Simulation at the two

worst case extremes (temperature, process, radiation (if applicable) and supply voltage) shall be identical with respect to

circuit operation (final state of each signal in each clock cycle must be identical).

MIL-STD-883F

METHOD 5010.4

18 June 2004

APPENDIX I

10.3 Layout verification

. The manufacturer shall retain the results of full mask level design rule checks, electrical rule

checks, and connectivity checks (see 10.1) for each application specific design. Rule checking will encompass the rules set

provided under 10.1 herein. The manufacturer will explain any rules not checked and all error reports produced by the

checker. The LVS checker will ensure that the layout matches exactly the schematic simulated by the ASIC designer. Final

layout verification results will not be required if the manufacturer's design methodology is "correct by construction." In this

case, the manufacturer will explain the methodology and rules used, as well as any rules not checked and all error reports

which were not corrected during construction of design.

10.4 Power routing simulation

. To be retained by manufacturer; derived from each final application specific electrical

design and layout. The worst case simulation of power buses shall show that at no time shall the localized bus current

density exceed specification for allowable current density of the power bus material. In addition, at no point in the power bus

shall voltage levels exceed design goals for IR drop values from the respective supply. Power routing simulation must be

based upon actual placement of cells within the array. Such a simulation may be driven by Monte Carlo methods, or in

conjunction with a digital simulator using the selected set of test vectors.

10.5 Cell design and simulation qualification

. Cell design and simulation qualification shall be accomplished in a two step

procedure consisting of:

a. Parameter verification/simulation verification, and

b. Functional verification.

A chip or set of chips, called the cell test chip set, shall be designed to provide access to a set of cells to test performance

characteristics. The cell test chip set design must be submitted to the qualifying activity for approval prior to use. The cell

test chip shall include as a minimum:

Description

Inverter

4-input NAND

2-input AND into 3-input NOR

D latch with active low reset

JK flip-flop with active low reset

TTL input buffer

CMOS input buffer

Output buffer

Three-state I/O buffer with pull-up

MIL-STD-883F

METHOD 5010.4

18 June 2004

APPENDIX I

The intent is to get a representative cross section of cell types (i.e., combinational, sequential, input, output). Chains shall

be formed (when necessary to avoid rise and fall time measurement problems) and actual performance data over the full

operating range shall be taken (a provision to extract for multiplexing and I/O buffer delay shall be included). Delay versus

metal wire length and fanout for the above cells shall be determined. The actual performance data shall be submitted to the

qualifying activity along with computer program simulation results. The actual performance data must be within the limits

predicted by the simulation. If multipliers are used to extrapolate performance at the temperature extremes, such multipliers

shall be verified as well.

In addition, for the above cells, a set of pins shall be provided on the test chip for observability. This will enable verification

of functionality of the cells. (Note: Inputs and outputs may be multiplexed).

10.6 CAD routing and post routing simulation

. A chip or set of chips shall be submitted for approval and used to qualify

the manufacturer's ability to perform routing and to accurately predict post routing performance. The manufacturer must

submit to the qualifying activity:

a. The actual measured performance data for each function over temperature and voltage.

b. The computer simulation performance prediction.

The two results will remain on file and the actual measured performances must fall between the simulation extremes.

20. APPLICABLE DOCUMENTS (This section is not applicable to this document.)

30. CERTIFICATION QUESTIONS

30.1 Cell libraries

a. Who is the source for your cell libraries?

Own organization?

Work station vendors?

Outside commercial vendors?

Universities?

b. What verification or certification is done for cell libraries, including those obtained from outside organizations? Are

macrocells implemented in silicon and verified for functionality and performance limits via actual hardware test? Is

only software simulation performed?

c. How are cell libraries controlled (e.g., level of documentation, maintenance and revisions, specifications,

additions)?

d. Provide company-approved cell library.

e. Identify those implemented and tested in silicon.

f. Is a designer allowed to tailor a macrocell or "roll his own" for a certain application? If so, how is the resulting

macro tested to insure there are no problems?