MIL- STD-883F 2004 TEST METHOD STANDARD MICROCIRCUITS.pdf - 第505页
MIL-STD-883F METHOD 3013.1 15 November 1974 1 METHOD 3013.1 NOISE MARGIN MEASUREMENTS FOR DIGI TAL MICROELECTRONIC DEVICES 1. PURPOSE . This method est ablis hes the means of measur ing the dc (st eady- st ate) and ac (t…
MIL-STD-883F
METHOD 3012.1
15 November 1974
2
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MIL-STD-883F
METHOD 3013.1
15 November 1974
1
METHOD 3013.1
NOISE MARGIN MEASUREMENTS FOR DIGITAL MICROELECTRONIC DEVICES
1. PURPOSE
. This method establishes the means of measuring the dc (steady- state) and ac (transient) noise margin of
digital microelectronic devices or to determine compliance with specified noise margin requirements in the applicable
acquisition document. It is also intended to provide assurance of interchangeability of devices and to eliminate
misunderstanding between manufacturers and users on noise margin test procedures and results. The standardization of
particular combinations of test parameters (e.g., pulse width, pulse amplitude, etc.) does not preclude the characterization of
devices under test with other variations in these parameters. However, such variations shall, where applicable, be provided
as additional conditions of test and shall not serve as a substitute for the requirements established herein.
1.1 Definitions
. The following definitions shall apply for the purposes of this test method:
a. Noise margin. Noise margin is defined as the voltage amplitude of extraneous signal which can be algebraically
added to the noise-free worst case "input" level before the output voltage deviates from the allowable logic voltage
levels. The term "input" (in quotation marks) is used here to refer to logic input terminals or ground reference
terminals.
b. DC noise margin. DC noise margin is defined as the dc voltage amplitude which can be algebraically added to the
noise-free worst case "input" level before the output exceeds the allowable logic voltage levels.
c. AC noise margin. AC noise margin is defined as the transient or pulse voltage amplitude which can be
algebraically added to the noise-free worst case "input" level before the output voltage exceeds the allowable logic
voltage levels.
d. Maximum and minimum. Maximum and minimum refer to an algebraic system where "max" represents the most
positive value of the range and "min" represents the least positive value of the range.
1.2 Symbols
. The following symbols shall apply for the purposes of this test method and shall be used in accordance with
the definitions provided (see 1.2.1, 1.2.2, and 1.2.3) and depicted on figures 3013-1, 3013-2, and 3013-3.
1.2.1 Logic levels
.
V
IL
max: The maximum allowed input LOW level in a logic system.
V
IL
min: The minimum allowed input LOW level in a logic system.
V
IH
max: The maximum allowed input HIGH level in a logic system.
V
IH
min: The minimum allowed input HIGH level in a logic system.
V
OL
max: The maximum output LOW level specified for a digital microelectronic device.
V
OL
max is also the noise-free worst case input LOW level, V
OL
(max) < V
IL
(max)
V
OH
min: The minimum output HIGH level specified for a digital microelectronic device.
V
OH
min is also the noise-free worst case input HIGH level, V
OH
(min) > V
IH
(min)
1.2.2 Noise margin levels
.
V
NL
: The LOW level noise margin or input voltage amplitude which can be algebraically added to V
OL
(max) before
the output level exceeds the allowed logic level.
V
NH
: The HIGH level noise margin or input voltage amplitude which can be algebraically added to V
OH
(min) before
the output level exceeds the allowed logic level.
V
NG+
: The positive voltage which can be algebraically added to the ground level before the output exceeds the
allowed logic level determined by worst case logic input levels.
*
MIL-STD-883F
METHOD 3013.1
15 November 1974
2
V
NG-
: The negative voltage which can be algebraically added to the ground level before the output exceeds the
allowed logic level determined by worst case logic input levels.
V
NP+
: The positive voltage which can be algebraically added to the noise-free worst case most positive power
supply voltage before the output exceeds the allowed logic level determined by worst case logic input levels.
V
NP-
: The negative voltage which can be algebraically added to the noise-free worst case most negative (least
positive) power supply voltage before the output exceeds the allowed logic level determined by worst case
logic input levels.
1.2.3 Noise pulse widths
.
t
PL
: The LOW level noise pulse width, measured at the V
IL
(max) level.
t
PH
: The HIGH level noise pulse width, measured at the V
IH
(min) level.
2. APPARATUS
. The apparatus used for noise margin measurements shall include a suitable source generator (see 2.1),
load (see 2.2), and voltage detection devices for determining logic state.
2.1 Source generator
. The source generator for this test shall be capable of supplying the required ac and dc noise
inputs. In the case of pulsed inputs the transition times of the injected noise pulse shall each be maintained to less than 20
percent of the pulse width measured at the 50 percent amplitude level. For the purpose of this criteria, the transition times
shall be between the 10 percent and 90 percent amplitude levels. The pulse repetition rate shall be sufficiently low that the
element under test is at steady-state conditions prior to application of the noise pulse. For the purpose of this criteria,
doubling the repetition rate or duty cycle shall not affect the outcome of the measurement.
2.2 Load
. The load for this test shall simulate the circuit parameters of the normal load which would be applied in
application of the device under worst-case conditions. The load shall automatically change its electrical parameters as the
device under test changes logic state if this is the normal situation for the particular device load. The load shall be paralleled
by a high impedance voltage detection device.
3. PROCEDURE
. The device shall be connected for operation using a source generator and load as specified (see 2),
and measurements shall be made of V
NL
, V
NH
, V
NG
, V
NP
, t
PL
, and t
PH
following the procedures for both ac noise margin and
dc noise margin (see 3.2 through 3.3.3).
3.1 General considerations
.
3.1.1 Nonpropagation of injected noise
. As defined in 1.1, noise margin is the amplitude of extraneous signal which may
be added to a noise-free worst case "input" level before the output breaks the allowable logic levels. This definition of noise
margin allows the measurement of both dc and ac noise immunity on logic inputs or power supply lines or ground reference
lines by detection of either a maximum LOW level or a minimum HIGH level at the output terminal. Since the output level
never exceeds the allowable logic level under conditions of injected noise, the noise is not considered to propagate through
the element under test.
3.1.2 Superposition of simultaneously injected noise
. Because the logic levels are restored after one stage, and because
the noise margin measurement is performed with all "inactive" inputs at the worst case logic levels, the proper system logic
levels are guaranteed in the presence of simultaneous disturbances separated by at least one stage.
3.1.3 Characterization of ac noise margin
. Although the purpose of this standard test procedure is to insure
interchangeability of elements by a single- point measurement of ac noise margin, the test procedure is well suited to the
measurement of ac noise margin as a function of noise pulse width. In particular, for very wide pulse widths, the ac noise
margin asymptotes to a value identically equal to the dc noise margin.